About Board routing restrictions of LPDDR4

[okamotosatoshi]

Hi There,

The documentation provides recommended routing requirements.

（Table 21. i.MX 8M Mini LPDDR4-3000 routing recommendations）

Only DQS ± 10ps is recommended for the data byte lane.

However, Table.23 can be found within 1ps in the data group.

Does the data group need to match within 1ps like CLK / DQS?

● i.MX 8M Mini Hardware Developer’s Guide:
　i.MX 8M Mini Hardware Developer’s Guide, User's Guide
　IMX8MMHDG Rev. 1, 08/2019

Best regards
- satoshi

[okamotosatoshi]

Hi Mrudang

Thank you for your answer！

We will try to match the delay time of the data lane as much as possible.

Best regards
- satoshi

[mrudang_shelat · Accepted solution]

Hi @okamotosatoshi,

Yes, As per Table-21, we need to match within +/-10ps, but if we are able to match within 1ps then it is the best. It is recommended too.

Regards,

Mrudang