About ASI master clock of MX6UL

[yuuki]

Dear all,

I want to use SAI of i.MX6UL.

I refer to Chapter 43 of RM.
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6ULRM.pdf
- Chapter 43 Synchronous Audio Interface (SAI)

I have some questions.

<Q1>
I understand the Master Clock of SAI is generated by SAIx_CLK_ROOT.
Is SAIx_CLK_ROOT connected directly with Master Clock of SAIx?

<Q2>
In MCLK Select field of I2Sx_TCR2 register, audio Master Clock option can be chosen.
However, I cannot find the explanation about these options.

Would you tell me the point where this is explained?

<Q3>
In MCLK Select of the I2Sx_RCR2 register, would you tell me the concrete clock name of "00:Bus Clock selected"?

May I have advice?

Best Regards,
Yuuki

[570035964]

Hi:

Why the SAI1_MCLK Can't output to the Pin.

my configuration:

Use Pad : CSI_DATA01,  Mode(ALT6), PAD_CTL (Pull up with 47kohm, SPEED_3_max_200MHz, Fast_Slew_rate)

The other signal of the SAI (include BCLK、SYNC、DATA) are all output correctly.

Help me out,Tks

[kenmeng]

HI

are you solved this problem?

i have same issue. if you solved,please share it with everyone！

[CarlosCasillas · Accepted solution]

Hi Yuuki

If you refer to section 18.3 “CCM Clock Tree” of the same Reference Manual you will see the origins and destinations of each clock signal, including SAI1_CLK_ROOT, SAI2_CLK_ROOT and SAI3_CLK_ROOT.

Then, on section 18.4, the Table 18-3 shows the CCM output clocks' system-level connectivity. The following picture shows the SAI’s clocks:

Hope this will be useful for you.
Best regards!
/Carlos

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[yuuki]

Dear CarlosCasillas-san,

Thank you for your support.

I understood that those clock were connected like the following figure.

- MCLK of each ASI is supplied from ASIx_CLK_ROOT.
- Clock source (SAIx_CLK_ROOT) is chosen by MSEL field.
- The Bus clock means AHB CLK(AHB_CLK_ROOT).

Is my understanding right?

Best Regards,

Yuuki

[CarlosCasillas]

Hi Yuuki,

Yes, you are right!

Best regards!
/Carlos

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------