About 24bit LCD panel connection for i.MX25

[yuuki]

Dear all,

We want to connect 24bit (RGB8bit) LCD panel to LCDC of i.MX25.

According to Table 33-3 in Reference Manual, it seems to be necessary to use 24 bpp AUS mode.

However, follows are explained in NOTE of Table 33-3.
"Need to add 24bpp paralled mode."

And, we found the following description.

In Figure 33-11, an LD [23:0] is listed.

LD18 to LD23 are multiplexed by other function pins.

We want to connect LCD in 24bit parallel, not AUS mode.
Does LCDC of i.MX25 support 24bit parallel connection?

If it is supported, would you teach the needed setting?

<Reference point>
IMX25RM.pdf(Rev2):
- Table 4-18. i.MX25 Detailed Pin Muxing(P.100-)
- Figure 33-11. LCDC Interface Signals(P.1042)
- Table 33-3. TFT Color Channel Assignments(P.1048)

Best Regards,
Yuuki

[Yuri · Accepted solution]

  In order to use of 24bpp (RGB888), please configure LD16:LD23

(which are multiplexed with FEC signals) for LCD (via IOMUX),

and LCDC Panel Configuration Register (LPCR), bit field BPIX.

   Also please pay attention on the next erratum.

ENGcm07723

LCDC/IOMUX: Default out of display pins does not match LCDC 16 bpp

mode in IOMUX.

http://cache.freescale.com/files/dsp/doc/errata/IMX25CE.pdf

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[yuuki]

Dear Yuri-san,

Thank you very much for your answer.

I have one question more.

I understand that RGB data is output on the following order.

Is this understanding right?

May I have advice?

Best Regards,

Yuuki

[Yuri]

RGB mapping is as following :

LD[23:16] – R[7:0]
LD[15:8] – G[7:0]
LD[7:0] – B[7:0]

(Red and Blue components should be swaped on Your figure.)

Regards,

Yuri.