About 10Mbps communication of ENET of i.MX6UL

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About 10Mbps communication of ENET of i.MX6UL

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yuuki
Contributor V

Dear all,

Our system uses the 100BASE-TX PHY.

When our system is connected to HUB of 10BASE-T, it cannot communicate.

In the case of 10MBps, we understand that ENET of i.MX6UL communicate at 2.5MHz to PHY.

However, ENET outputs data at 25MHz.

In the case of 10MBps(2.5MHz operation), should we set the MII_SPEED field of the ENETx_MSCR register in 0x4?

IMX6ULRM.pdf(Rev0)

- 23.5.7 MII Speed Control Register (ENETx_MSCR)

- Table 23-2. Programming Examples for MSCR

May I have advice?

Best Regards,

Yuuki

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Yuri
NXP TechSupport
NXP TechSupport

Hello, Yuuki-san !

  According to Table 23-1 (ENET External Signals) of the i.MX6 D/Q RM, ENET_RX_CLK

(GPIO_18) signal is used in MII mode as a timing reference for RX_EN, RX_DATA[3:0],

and RX_ER. Is it so on Your board ?

  Also, please refer to section 23.5.7 [MII Speed Control Register (ENET_MSCR)] of the RM.

Regards,

Yuri.

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b36401
NXP TechSupport
NXP TechSupport

Please try to use some another (more intelligent) ehternet hub.

The PHY in i.MX6 is starting on 100MBps speed by default.

Then if the hub i.MX6 is connected to reports that it supports only 10MBps i.MX6 switches to 10MBps speed.

However some hubs do not report it and simply wait for 10MBps connection.

In this case the connection fails.

Have a great day,

Victor

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yuuki
Contributor V

Dear Victor-san,

We observed a waveform.

CLK from PHY is 2.5MHz.

However, Output data from i.MX6 is 25MHz.

MII waveform.png

Furthermore, we found midpoint potential existing on Tx and Rx.

Midpoint potential on Tx and Rx..png

By these waveforms, we think that we overlook some setting.

Would you tell me the register whom we should confirm?

We need the solution ASAP.

Your kind helps would be greatly appreciated.

Best Regards,

Yuuki

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

Would You please try the following in order to configure the ENET for 10 Mbit

operation.

# ethtool -s eth0 autoneg off
# ethtool -s eth0 speed 10

Regards,

Yuri.

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yuuki
Contributor V

Dear Yuri-san,

Thank you for your support.

> # ethtool -s eth0 autoneg off

> # ethtool -s eth0 speed 10

=>

We are going to try these commands

In our test, we found RMII working with our board.

(but, MII does not work)

We have more questions.

(1)

Does NXP test MII operation?

(2)

In RMII operation, setting of the PAD was necessary.

> ENET1_RX_DATA0  ALT=0  PAD=0x00002020

> ENET1_RX_DATA1  ALT=0  PAD=0x00002020

> ENET1_RX_EN     ALT=0  PAD=0x00002020

> ENET1_TX_DATA0  ALT=0  PAD=0x00002020

> ENET1_TX_DATA1  ALT=0  PAD=0x00002020

> ENET1_TX_EN     ALT=0  PAD=0x00002020

> ENET1_TX_CLK    ALT=0  PAD=0x00002020

> ENET1_RX_ER     ALT=0  PAD=0x00002020

A default value of BSP is PAD=xxB0.

In this case TXD seems to work at 100MHz in spite of LCK=50MHz.

we understand that the setting of the PAD has nothing to do with the operating frequency of TXD.

We do not know what is a cause.

What should we confirm to operate RMII correctly?

Could you give me some advice?

Best Regards,

Yuuki

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Yuri
NXP TechSupport
NXP TechSupport

Hello, Yuuki-san !

  According to Table 23-1 (ENET External Signals) of the i.MX6 D/Q RM, ENET_RX_CLK

(GPIO_18) signal is used in MII mode as a timing reference for RX_EN, RX_DATA[3:0],

and RX_ER. Is it so on Your board ?

  Also, please refer to section 23.5.7 [MII Speed Control Register (ENET_MSCR)] of the RM.

Regards,

Yuri.

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yuuki
Contributor V

Dear Yuri-san,

Thank you for your support.

As a result of having investigated it, we found an MAC address not having been correct setting.
The problem was settled by correcting an MAC address.

We appreciate your kind response.

Best Regards,
Yuuki

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Yuri
NXP TechSupport
NXP TechSupport

:-)

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yuuki
Contributor V

Dear Victor-san,

Sorry for pushing you,  how about the situation afterward?

Please advise of your findings.

Best Regards,

Yuuki

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yuuki
Contributor V

Dear Victor-san,

Thank you for your support.

About register setting, we set it as follows.

- IOMUXC_GPR_GPR1.ENET1_TX_CLK_DIR = 0 (output disable)

- IOMUXC_GPR_GPR1.ENET1_CLK_SEL = 1

- CCM_ANALOG_PLL_ENET1_ENET0_DIV_SELECT = 00 (25MHz)

Would you tell me if there is the additional register that we have to set?

Best Regards,

Yuuki

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yuuki
Contributor V

Who can answer about this question?

Would you help me?

Best Regards,

Yuuki

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