ALSA i2s-master on 3.10.17

[joshkurland]

Hello,

I am developing an ALSA audio driver in 3.10.17 which will drive a GS1672 HD-SDI transmitter with audio embedding over i2s.  I have written the new codec and machine layers based on the imx-sgtl5000 reference design, but I am running into a dma issue when I use the new sound device with an application such as gstreamer or aplay. 

The ALSA driver gets probed and registered successfully:

   imx-gs1672 sound.22:  gs1672 <-> 2028000.ssi mapping ok

   ...   

   ALSA device list:

     #0: imx-gs1672

     #1: imx-spdif

     #2: imx-hdmi-soc

$ aplay -D hw:0,0 piano2.wav

Playing WAVE 'piano2.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo

aplay: pcm_write:1262: write error: Input/output error

I have traced the bug to fsl_ssi_trigger(), the error appears to occur right after

   [fsl_ssi_trigger]

   playback write error (DMA or IRQ trouble?)

   [fsl_ssi_trigger]

   [imx_gs1672_free]

The host (imx6q) has been configured to operate as i2s-master in order to transmit the bit and LR clocks to the GS1672 audio chip.  The GS1672 is not able to produce a clock of its own, and must be used as a slave.  Therefore the dai_fmt is set to use SND_SOC_DAIFMT_CBS_CFS, and I have flipped the audmux int and ext ports.  In the device tree, ssi1 has been changed from i2s-slave to i2s-master.  What other changes are necessary to support i2s-master? 

Recently I have noticed commits in Linux mainline addressing dma issues and i2s-master support in /sound/soc/fsl_ssi.c.  This makes me wonder, is i2s-master actually possible on 3.10.17?

Thank you,

Josh K.

[saurabh206]

Hi,

Josh

You need to verify clock setting properly.

According to me MCLK and bit clock should be generated from same reference clock.

You can refer IMX6DQRM.pdf  60.7.4 SSI Clocking.

Thanks

Saurabh

[joshkurland]

Hello Saurabh,

Thank you for responding.  I am rather new to ALSA and the audio capabilities of the imx6 platform.  Is it possible for you to walk me through the steps to generate and verify the SSI clocks?

At the core, I need to decode an mpg source and send the audio to my embedder chip.  According to the IMX6DQRM rev2 Chapter 61.8.1 (SSI Operating Modes), the SSI should be using Network Mode, I2S master.  On boot SSI1_SCR is set to 0x000000b8: I2S_MODE is i2s-master and NET is enabled.  After I run an application with my sound device, the register changes to 0x000005d0.  It seems that fsl_ssi_startup() in fsl_ssi.c is resetting the register "Program the SSI into I2S Slave Non-Network Synchronous mode".  I will continue to investigate further.

Is i2s-master mode in 3.10.17 known to function?  If so, can a tutorial or documentation be provided? 

Thank you,

Josh K.

[joshkurland · Accepted solution]

I back-ported patches for fsl_ssi.c from 3.18 into the 3.10.17 release.  I2S-Master now works! 

[caiopereira]

Josh, could you share the patch with us?

Regards,

Caio Pereira