8MNANOD3L-EVK power consumption higher than AN13367 for Low Power Suspend Mode

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8MNANOD3L-EVK power consumption higher than AN13367 for Low Power Suspend Mode

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SharmaS
Contributor II

Hello,

We recently purchased 8MNANOD3L-EVK. It shipped with image Linux release 5.4.70. I upgraded (eMMC using uuu) it to NXP pre-built image of release 5.10.52_2.1.0 from here since the App Note AN13367 (i.MX 8M Nano Ultra Lite Power Consumption Measurement) states that power numbers were measured using 5.10.52_2.1.0. Intention here is to establish common baseline before adding custom use cases simulation on top to measure power for those cases.

Here's the rework details to measure power according to AN13367.

  1. For VDD_SOC_0V9, split the connection and added a 0.5ohm Sense Resistor after Capacitor C283
  2. For NVCC_DRAM_1V35, split the connection and added a a 0.1ohm Sense Resistor after Capacitor C318

We're unable to get VDDA_1V8 out since it's very difficult to do the rework in house for this rail.

I am getting below numbers with Low Power Suspend Mode - 4.1.1 from AN13367 (Linux suspend to RAM using command "echo mem > /sys/power/state/" on Linux console)

Supply domainVoltage (V)Current - I (mA)Power - P(mW
NVCC_1V351.3570.294.8
VDD_SOC_0V90.752.82.1


Please note the numbers for NVCC_DRAM_1V35 particularly. In the Low Power Suspend Mode it is over 5 times higher than published numbers in AN13367.

Would you please help in ascertaining why the additional draw on NVCC_DRAM_1V35 using NXP pre-built image? How would you recommend to lower to published numbers? Is there a different rework to measure power?

PS: I tried power measurements using Linux release 5.4.70 and 6.1.22 in addition to 5.10.52. The measured power is not identical but it very close to above.

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SharmaS
Contributor II

We modified the re-work as follow by inferring from AN12778 rework.

  1. For VDD_SOC_0V9, split the connection and added a 0.025ohm Sense Resistor after Capacitor C283
  2. For NVCC_DRAM_1V35, split the connection and added a a 0.025ohm Sense Resistor after Capacitor C318.

This shows power numbers much closer to AN13367.

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SharmaS
Contributor II

We modified the re-work as follow by inferring from AN12778 rework.

  1. For VDD_SOC_0V9, split the connection and added a 0.025ohm Sense Resistor after Capacitor C283
  2. For NVCC_DRAM_1V35, split the connection and added a a 0.025ohm Sense Resistor after Capacitor C318.

This shows power numbers much closer to AN13367.

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SharmaS
Contributor II

The App Note AN 13367 title states it is for i.MX8M Nano Ultra lite processor. The section 3.4 of AN13367 states what software and hardware is used to perform measurements which is 

3.4 Hardware and software used
The software versions used for the measurements are:
• i.MX 8M Nano UL DDR3L EVK Platform with the software release: L5.10.52_2.1.0.
• The measurements were performed using the 34470A 6½ digital multimeter.

. The table showing power consumption states first supply domain as NVCC_DRAM_1V35.  Are you implying it's incorrect and lpddr4 board was used to publish data for 8MNUL?

What more information I can provide to get on same page with respect to revision of the Hardware? I see following when it boots with 6.1.22 release pre-built image,

U-Boot 2023.04-lf_v2023.04+gaf7d004eaf (Jun 06 2023 - 14:59:40 +0000)

CPU: i.MX8MNano UltraLite Quad rev1.0 1400 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 30C
Reset cause: POR
Model: NXP i.MX8MNano DDR3L EVK board
DRAM: 992 MiB
TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C1 0x52]
Power supply on USB2
TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C1 0x50]
Core: 186 devices, 27 uclasses, devicetree: separate
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... *** Warning - bad CRC, using default environment

 

I am certainly not expecting that my measurements exactly match what's published but I expect them to similar. We have used a few NXP processors for several years and we have found in past in house measurements trends similar to published App Note. Please help me uncover what I am missing.

 

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Chavira
NXP TechSupport
NXP TechSupport

Hi @SharmaS!

Yes you are right!
Sorry for the mistake!

The board used for that purpose was the imx8mn UL ddr3.

I don’t know if the way to measure the current could affect the measure.

3.5 Measuring points on the EVK platform
To measure the power consumption, do the rework first. Split the connection between the PMIC output inductor and the CPU and connect the NXP power consumption test tool in series. The power data is sampled by the tool and calculates the average current and power consumption.

We do the measure directly with the multimeter.

Could you try doing the measure in the same way, please?

 

Note:

For all use cases, the platform boots from an SD card with the default dtb configuration in the U-Boot stage.
For the DDR3L EVK Board, check whether the default dtb file is imx8mn-ddr3l-evk.dtb for the DDR3L EVK Board:
printenv fdt_file

If the default dtb file is not imx8mn-ddr3l-evk.dtb, set it as follows:

setenv fdt_file “imx8mn-ddr3l-evk.dtb” saveenv

Best Regards!

Chavira

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SharmaS
Contributor II

Thank you for your response.

We followed the same instruction and measured the current using Keysight 61/2 digit benchtop Digital Multimeter. If you'd like me to test with NXP test tool, it is unclear from the App Note which test tool, how to set up, etc. Is there a document that you can point me to?

I ensured that I use the same device tree blob imx8mn-ddr3l-evk.dtb before I start measurement. 

Is there anything in below rework that you can help identify that might be causing higher drain?

  1. For VDD_SOC_0V9, split the connection and added a 0.5ohm Sense Resistor after Capacitor C283
  2. For NVCC_DRAM_1V35, split the connection and added a 0.1ohm Sense Resistor after Capacitor C318

Is there a different rework that NXP team recommends? Like different sense resistor value, etc.

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Chavira
NXP TechSupport
NXP TechSupport

Hi @SharmaS !
We do the measurement like the schematic attached, probably adding the resistors could be wrong in this measurement.
Please try to do the measurements like the Application Note and if the problem persists let me know.
Best Regards!
Chavira

Chavira_1-1695404507325.png

 

 

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Chavira
NXP TechSupport
NXP TechSupport

Thank you for contacting NXP Support!

The Application Notes are a guide on how to do something in particular.

In this case, when our team does this Application Note we obtain those results, but it can depend on the revision of the board, the peripherals connected, etc.

The section 4.1.1 doesn’t specify what is the board used for this test but I assume that we use the lpddr4 board for the test because the section 4.1.3 specify the ddr3 board.

Best Regards!

Chavira

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