Hi,
I'm using 6sl with a xilinx fpga. The xilinx fpga provides the BOOT_CFG signals during bootup/POR for the 6sl. There is a pin called fpga_suspend that controls whether the xilinx fpga gets suspended (low power state for the fpga) or not. This signal is active-high. During bootup of 6sl, before u-boot and kernel, that pin needs to be low otherwise the fpga would get suspended and cause problems during bootup. Therefore, I used an external pulldown on that pin. That solves the issue for before the 6sl gets to u-boot/kernel.
Now, after bootup, when we want the system to go into a low power state/s3/suspend-to-ram, we use the 6sl to drive the fpga_suspend pin high and this causes the fpga to get suspended. Everything is fine for this. Then the next stage is for the 6sl to go into low power state/s3. But when it does this, that pin which is gpio and is in the dormant power domain goes low (because of the external pulldown) and so now the 6sl is suspended but the fpga has been woken up.
I can't get rid of the external pulldown because then I have problems during bootup. I was hoping to use something like keeper to keep the pin high during 6sl suspend state, but I'm having some trouble with that. The datasheet says:
-
When Keeper is enabled, the pull-up and pull-down are disabled, and the output value of
the pad depends on the Keeper. The output keeper is powered by OVDD. When the core
VDD is powered down or the first inverter is tri-stated, the pad’s state can be kept.
Keeper and Pull can’t be enabled together.
-
• Pull-up, pull-down, and pad keeper are disabled in output mode.
"
My question is what happens to a gpio output pin with keeper set (PKE) that has been driven high , and then the system goes into s3. Does the keeper come into effect during suspend? Or does it not come into effect because the pin was an output pin?
I would also be happy to try out other ideas that could solve my problem. I need to keep that pin high during suspend but keep it low during bootup (before u-boot/kernel).
Thanks!
