512MB IMX7 DDR3 Configuration

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512MB IMX7 DDR3 Configuration

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gabrielebettoni
Contributor II

HI,

we have developed a custiom IMX7 Dual with the DDR3 connections and Power supply based on the NXP SabreSD reference design,

we have changed using the excel register aid the script to start the initialization of the device,with the roduced address space of our RAM (2x MT41K128M16), in order to execute the DDR3 stress tool V.2.7.

This are the values from the register aid:

#=============================================================================
# DDR Controller Registers
#=============================================================================
# Memory type: DDR3
# Manufacturer: Micron
# Device Part Number: MT41K128M16HA-125:E
# Clock Freq.: 533MHz
# Density per CS in Gb: 4
# Chip Selects used: 1
# Number of Banks: 8
# Row address: 14
# Column address: 10
# Data bus width: 32
# ROW-BANK interleave: DISABLED
#=============================================================================

memory set 0x30391000 32 0x00000002 # deassert presetn
memory set 0x307A0000 32 0x01040001 # DDRC_MSTR
memory set 0x307A0064 32 0x0040002B # DDRC_RFSHTMG
memory set 0x307a0490 32 0x00000001 # DDRC_PCTRL_0
memory set 0x307A00D4 32 0x00690000 # DDRC_INIT1 (if using LPDDR3/LPDDR2, this line is automatically commented out)
memory set 0x307A00D0 32 0x00020083 # DDRC_INIT0
#memory set 0x307A00D8 32 0x00000000 # DDRC_INIT2 (if using DDR3 or LPDDR3 this line is automatically commented out)
memory set 0x307A00DC 32 0x09300004 # DDRC_INIT3
memory set 0x307A00E0 32 0x04080000 # DDRC_INIT4
memory set 0x307A00E4 32 0x00100004 # DDRC_INIT5
memory set 0x307A00F4 32 0x0000033F # DDRC_RANKCTL
memory set 0x307A0100 32 0x09081109 # DDRC_DRAMTMG0
memory set 0x307A0104 32 0x0007020D # DDRC_DRAMTMG1
memory set 0x307A0108 32 0x03040407 # DDRC_DRAMTMG2
memory set 0x307A010C 32 0x00002006 # DDRC_DRAMTMG3
memory set 0x307A0110 32 0x04020205 # DDRC_DRAMTMG4
memory set 0x307A0114 32 0x03030202 # DDRC_DRAMTMG5
#memory set 0x307A0118 32 0x02020005 # DDRC_DRAMTMG6
#memory set 0x307A011C 32 0x00000202 # DDRC_DRAMTMG7
memory set 0x307A0120 32 0x00000802 # DDRC_DRAMTMG8
memory set 0x307A0180 32 0x00800020 # DDRC_ZQCTL0
#memory set 0x307A0184 32 0x02000100 # DDRC_ZQCTL1
memory set 0x307A0190 32 0x02098204 # DDRC_DFITMG0
memory set 0x307A0194 32 0x00030303 # DDRC_DFITMG1
memory set 0x307A01A0 32 0x80400003 # DDRC_DFIUPD0
memory set 0x307A01A4 32 0x00100020 # DDRC_DFIUPD1
memory set 0x307A01A8 32 0x80100004 # DDRC_DFIUPD2
memory set 0x307A0200 32 0x00000015 # DDRC_ADDRMAP0
memory set 0x307A0204 32 0x00161616 # DDRC_ADDRMAP1
memory set 0x307A020C 32 0x00000000 # DDRC_ADDRMAP3
memory set 0x307A0210 32 0x00000F0F # DDRC_ADDRMAP4
memory set 0x307A0214 32 0x04040404 # DDRC_ADDRMAP5
memory set 0x307A0218 32 0x0F0F0404 # DDRC_ADDRMAP6
memory set 0x307A0240 32 0x06000604 # DDRC_ODTCFG
memory set 0x307A0244 32 0x00000001 # DDRC_ODTMAP

#=============================================================================
# PHY Control Registers
#=============================================================================

memory set 0x30391000 32 0x00000000 # deassert presetn
memory set 0x30790000 32 0x17420F40 # DDR_PHY_PHY_CON0
memory set 0x30790004 32 0x10210100 # DDR_PHY_PHY_CON1
#memory set 0x30790008 32 0x00010000 # DDR_PHY_PHY_CON2 (if using DDR3 this line is automatically commented out)
memory set 0x30790010 32 0x00060807 # DDR_PHY_PHY_CON4
memory set 0x307900B0 32 0x1010007E # DDR_PHY_MDLL_CON0
#memory set 0x3079001C 32 0x01010000 # DDR_PHY_PHY_RODT_CON0 (if using DDR3 this line is automatically commented out)
memory set 0x3079009C 32 0x00000D6E # DDR_PHY_DRVDS_CON0

#memory set 0x30790078 32 0x00000001 # DDR_PHY_WR_LVL_CON3 - Optional write leveling resync enable, uncomment to invoke
#memory set 0x3079006C 32 0x00000000 # DDR_PHY_WR_LVL_CON0 - Optional write leveling values for each byte lane, uncomment to invoke
#memory set 0x30790078 32 0x00000000 # DDR_PHY_WR_LVL_CON3 - Optional write leveling resync disable, uncomment to invoke

memory set 0x30790030 32 0x08080808 # DDR_PHY_OFFSET_WR_CON0
memory set 0x30790020 32 0x08080808 # DDR_PHY_OFFSET_RD_CON0
memory set 0x30790050 32 0x01000010 # DDR_PHY_OFFSETD_CON0
memory set 0x30790050 32 0x00000010 # DDR_PHY_OFFSETD_CON0
memory set 0x30790018 32 0x0000000F # DDR_PHY_LP_CON0
memory set 0x307900C0 32 0x0E407304 # DDR_PHY_ZQ_CON0 - Start Manual ZQ
memory set 0x307900C0 32 0x0E447304
memory set 0x307900C0 32 0x0E447306
memory set 0x307900C0 32 0x0E447304
# <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
memory set 0x307900C0 32 0x0E407304 # DDR_PHY_ZQ_CON0 - End Manual ZQ


#=============================================================================
# Final Initialization start sequence
#=============================================================================

memory set 0x30384130 32 0x00000000 #Disable Clock
memory set 0x30340020 32 0x00000178 # IOMUX_GRP_GRP8 - Start input to PHY
memory set 0x30384130 32 0x00000002 #Enable Clock
# <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point.

The Initial script is downloaded correctly on the device via USB and we are able to read/write registers...
But when we try to do the calibration or the DDR test the software hangs, with all the buttons disabled and no more feedback from the console, in order to try to better investigate the issue we have already checked:

- Schematic and Layout (As in the Sabre SD)

- Power up sequence

- Monitor the status of PLLs via CLK1 output reading and writing registers via the stress tool, and all seems good.

We have leaved, as in the reference design, the poissibility to use double die DDR, connecting the balls J1, J9, L1, L9 on the DDR3 chips, that should be left unconnectes, this could be the root cause for this behaviour?

Looking forward for comments and opinions,

Regards,

G.

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1 Solution
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gabrielebettoni
Contributor II

Hi Yuri,

the root cause has been found, the JTAG_MOD in our board is configured for Boundary scan access, so it has a pull up.

Changing this pin to a pull down has solved, the stress tool works and pass!!!

Thanks for your support,

Regards,

G.

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5 Replies
434 Views
sidebranch
Contributor II

We used 2x MT41K128M16 as well, but in 1066 mode.

I verified also against your settings. You might want to check your tRAS value. It seems a bit too small even for 1333 mode.

Rest seems OK! Thanks for posting the settings.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   Please try the recent i.MX7D DRAM Register Programming Aid 

I think the following parameters should be used:

pastedImage_2.png

Have a great day,
Yuri

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gabrielebettoni
Contributor II

Hello, thanks for the proposal,

I have already used the latest register programming Aid, looking deeper at the problem it seems that the DDR PHY controller doesn't finish the Zq calibration task, debugging using the linux usb loader and trying to modify the DCD table when we ask to check the end of Zq calibration, the check fails:

DATA 4 0x307900c0 0x0e407304 
DATA 4 0x307900c0 0x0e447304 
DATA 4 0x307900c0 0x0e447306 

CHECK_BITS_SET 4 0x307900c4 0x1

What could be the cause of such a problem at this step it could not be related to the RAM external connections of timing, it seems to me that it is something that belongs to the internal DDR PHY.

 

Regards,

G.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  please verify if Your board design meets DDR routing rules in section 3.4.1 of 

“Hardware Development Guide for i.MX7Dual and 7Solo Applications Processors”
http://www.nxp.com/assets/documents/data/en/user-guides/IMX7DSHDG.pdf

http://www.nxp.com/assets/documents/data/en/user-guides/IMX7DSHDG.pdf 


Regards,

Yuri.

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435 Views
gabrielebettoni
Contributor II

Hi Yuri,

the root cause has been found, the JTAG_MOD in our board is configured for Boundary scan access, so it has a pull up.

Changing this pin to a pull down has solved, the stress tool works and pass!!!

Thanks for your support,

Regards,

G.