Below are considerations how to get 15 MHz of minimal value for IPUx_HSP_CLK_ROOT;
IPUx_HSP_CLK_ROOT is reference clock for display / pixel clock. The display clock is (micro)programmable,
and its value may be less than IPUx_HSP_CLK_ROOT. Theoretically it can achieve tens KHz.
Another thing, that the display frequency duty parameter may be not 50%.
According to the linked below Community thread :
" Referring to Figure 18-2, IPU1_HSP_CLK_ROOT may be selected to have 1 of 4 sources. These sources are highlighted in yellow on the northwest corner of the page and the previous paragraph states these are max values. Possible sources are 540, 528, 396, and 480 MHz. The 480 MHz is divided by 4 before the selector, so winds up being 120 MHz. Per the diagram, these are all divided by 2 for IPU1_HSP_CLK_ROOT. The result is 270, 264, 198, and 60 MHz choices". Note, really 120 MHz may be divided by 8 (please refer to CCM_CSCDR3 field descriptions
in the Reference Manual).
So, 15 MHz is minimal value for IPUx_HSP_CLK_ROOT. Next, we should consider parameter IP5 (Display interface clock period Tdicp) and IP6 (Display pixel clock period) in the i.MX6 Datasheets. Minumal period for display clock is defined by parameter DI_CLK_PERIOD, which is programmable.
Please refer to section 37.4.10.3 (Timing generator) of the i.MX6 DQ Reference Manual. Display interface clock period is defined by 8-bit divider (interger part) ; this means minimal clock is ~60 KHz.
"Q&A: What are the maximum HSP_CLK frequency values?"
< https://community.freescale.com/docs/DOC-98282 >
Also, please take a look at Chapter 18 (Configuring the IPU Driver) of the "iMX6_Firmware_Guide.pdf"
in the Platfrom SDK package.
< https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null >
