32-beat burst transfer with SDMA in i.MX6Q.

[keitanagashima]

Dear Sir or Madam,

Hi.

I'd like to realize below transfer om i.MX6Q.

4Byte(32bit) : 32-beat burst transfer (=128Byte)

[Observed Result]

Burst Access by using SDMA.

Write:

DRAM to EIM(0x08000000) --> (7 beat + 1 beat) x 4

DRAM to EIM(0x0C000000) --> (7 beat + 1 beat) x 4

Read:

DRAM to EIM(0x08000000) --> (8 beat) x 4

DRAM to EIM(0x0C000000) --> (8 beat) x 4

[Question]

Refer to 55.4.3.1 Burst DMA Unit in MCIMX6DQRM(Rev.1).

----

Perform up to 8-beat read and write bursts to the ARM platform memory, which

optimizes throughput when accessing SDRAM-type devices because of an internal,

36-byte FIFO

----

=Q1=

When using SDMA, is the 8-beat burst transfer the maximum?

Is there a way of realizing 32-beat burst transfer?

=Q2=

In case of "Write" operation, it became (7 beat + 1 beat) x 4.

What setting is necessary for the 8-beat burst transfer?

Keita

[leige-b42127]

Q1:yes, 8 beat is the maximum.

Q2:maybe nic301bus, not sure, have to check

[keitanagashima]

Could someone follow up the question?

Keita

[YixingKong]

Keita

Our engineer has below answers. Please contact us again if you need further help.

------------------------------------

Q1:yes, 8 beat is the maximum.

Q2:maybe nic301bus, not sure, have to check

------------------------------

Thanks,

Yixing

[gangli]

Yixing,

Do you or your engineer has any example that use sdma with eim ?  I tried based on imx-sdma.c and dmaengine in latest kernel to transfer data between eim and ddr, but failed. There was no access to eim when i submit dma to copy data from ddr to eim, because there was no bclk out. Can you give me some help?

Thanks,

Gang

[leige-b42127]

we have no such example

[YixingKong]

Keita

Your DI has been assigned to an enginer and will be answered as soon as something is avaialble.

Thanks,

Yixing