Hello,
We're trying to generate DDR configuration for our i.MX8M Nano board with 2GB Micron DDR4 DRAM. The DRAM datasheet is available at https://www.micron.com/products/dram/ddr4-sdram/part-catalog/mt40a1g16knr-075
Attached you can find our PRA Tool configuration. The problem is that DDR Stress test tool V3.10 fails to properly recognize DRAM size (1GB instead of 2GB): The output of the tools is :
*************************************************************************
MX8 DDR Stress Test V3.10
Built on Feb 5 2020 13:02:45
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 1500MHz
DDR Clock: 1200MHz
============================================
DDR configuration
DDR type is DDR4
Data width: 16, bank num: 8
For DDR4, bank num is the total of 2 bank groups and 4 banks per group
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1024MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
============================================
I'd appreciate the review of our configuration.
Thanks a lot.
