Hi,
We are using MIMXRT1051CVL5B in our design and noticed that we have 1V leakage on DCDC_IN/ VDDA_ADC_3P3/ NVCC_X/ VDD_High_IN until PMIC_ON_REQ EN is asserted.
* DCDC_IN/ VDDA_ADC_3P3/ NVCC_X/ VDD_High_IN are connected to the same rail +V3.3_MAIN that is enabld to 3.3V after PMIC_ON_REQ EN is asserted.
Pink= +V3.3_MAIN, Blue= 3.3_SNVS:
We removed all the related ICs on the board (beside the MCU) to be sure we didn't short the +V3.3_MAIN to another rail.
the leakage occurs only when the SNVS rail is up
Can you please help find the reason why could it happen?
Solved! Go to Solution.
Could you share the schematic to us?
problem has solved