1GB DRR3 Chips x2 Nos Layout with IMX6 Quad Processor

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1GB DRR3 Chips x2 Nos Layout with IMX6 Quad Processor

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emilzachariageo
Contributor II

Hi Team,

In our new Dual Camera project, we're using 2GB DDR3L memory(1GB x16 DDR3L chips, 2Nos) with IMX6 Quad processor. We had earlier used 2 Nos 256MB DDR3L chips (total 512MB RAM) interfaced with IMX6 Solo processor in a Thermal camera project which is under production now. We've started the layout work for the IMX6 - DRAM interface for new Dual Camera project. As we donot have enough time, our plan is to use existing 2x 256MB DDR3 routing for new 2x 1GB DDR3 routing. So, we'll be using only 32 bit data bus amoung the 64 bits available. We found 3 new signals ODT1, CS1#, CKE1 in new 1GB DDR3L chips when compared to old 256MB chips. As we checked, it is hard to match the length of these signals to the clock signals already routed. Can you please advise us on how much length tolerance we can route these new signals compared to the clock signals?

Thanks in advance.

Emil Zacharia George

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  Please follow  Chapter 3 (i.MX 6 Series Layout Recommendations) of the Hardware Development Guide for i.MX6.

In particular - section 3.5 (DDR routing rules).

https://www.nxp.com/doc/IMX6DQ6SDLHDG


Have a great day,
Yuri

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emilzachariageo
Contributor II

Hello Yuri,

Thanks.

We found this.

But, our ODT1, CKE1 and CS1# signal lengths are more than Maximum clock

length by about 200 mils.

Will it be an issue or will it work?

Warm Regards.

Emil Zacharia George | Senior Hardware Design Engineer

*Mob: +91 **9061665533 *| Skype: emilgeorge93

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   For assurance, please try simulation of the DDR signals for Your board, using IBIS models.

Regards,

Yuri.

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emilzachariageo
Contributor II

Hi Yuri,

Thanks for the suggestion.

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