16bit BT1120 does not work on MX6Q

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16bit BT1120 does not work on MX6Q

2,672 Views
RobbieJiang
Contributor IV

Hi,

I'm currently working on capturing data from ADV7611,

which is connected to CSI0 of MX6Q.

The input of adv7611 is 1080P@60HZ,

the output of adv7611 is 16bit BT1120 SDR format,

By now, we can't capture any data from CSI0 port.

Here I have some questions:

1.  BT1120 standard requires the each video timing reference word to be 10bits.

And according to imx6 RM, page 3252,  for BT1120, bit[0-29] of register IPUx_CSI0_CCIR_CODE_3

should contain the CCIR pre command, which  should be 0x3FF00000.

However, in current LTIB L3.0.35_4.1.0_130816, driver/mxc/ipu3/ipu_capture.c,

when the CSI clock mode is IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,

0xFF0000, instead of 0x3FF00000,  is written into register CSI_CCIR_CODE_3.

Obviously, this is quite different from what is required by BT1120 standard and the imx61 RM.

So what should be the correct value to be written into CSI_CCIR_CODE_3?

2.  CSI_CCIR_CODE1 and CSI_CCIR_CODE2 should also be correctly setup to make BT1120 work.

For 1080P, we only concern on CS

Hi,

I'm currently working on capturing data from ADV7611,

which is connected to CSI0 of MX6Q.

The input of adv7611 is 1080P@60HZ,

the output of adv7611 is 16bit BT1120 SDR format,

By now, we can't capture any data from CSI0 port.

Here I have some questions:

1.  BT1120 standard requires the each video timing reference word to be 10bits.

And according to imx6 RM, page 3252,  for BT1120, bit[0-29] of register IPUx_CSI0_CCIR_CODE_3

should contain the CCIR pre command, which  should be 0x3FF00000.

However, in current LTIB L3.0.35_4.1.0_130816, driver/mxc/ipu3/ipu_capture.c,

when the CSI clock mode is IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,

0xFF0000, instead of 0x3FF00000,  is written into register CSI_CCIR_CODE_3.

Obviously, this is quite different from what is required by BT1120 standard and the imx61 RM.

So what should be the correct value to be written into CSI_CCIR_CODE_3?

2.  CSI_CCIR_CODE1 and CSI_CCIR_CODE2 should also be correctly setup to make BT1120 work.

For 1080P, we only concern on CSI_CCIR_CODE1 register.

The question is , what is the correct order  ( of  'F' 'V' 'H' )  for

field CSI0_STRT_FLD0_ACTV,  CSI0_END_FLD0_ACTV and

CSI0_STRT_FLD0_BLNK_1ST?

Is it  'H-V-F' or 'F-V-H'?

What is the correct bit order?

Fo BT656 interleaved mode, seems the correct order is 'H-V-F'.

Does it still hold for BT1120?

3. We have set up adv7611 to output data in 16bit YUV422 format.

On page 37.4.3.9  of imx6 RM,  there is a short section about "16 bit camera support".

16 bit YUV422:

"

In this mode the CSI receives 2 components per cycle. The CSI is programmed to

accept the data as 16 bit generic data. The captured data will be stored in the memory

through the SMFC. The IDMAC needs to be programmed to store 16bit generic data.

When the data is read back from the memory for further processing in the IPU it will

be read as YUV422 data.

Does it mean that field  CSI0_SENS_PRTCL in register  IPUx_CSI0_SENS_CONF

has to be "011"  in order to accept Bayer or Generic data?

And also the input chanel must be from CSI to memory directly, and no IC can be used?

And how to program IDMAC in order to store 16bit generic data,

so that when the data is read back as YUV422 data?

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6 Replies

139 Views
RobbieJiang
Contributor IV

FYI,  here is the data bus connection between adv7611 and mx6q.

We connect ADV7611's P0-P15 to mx6's CSI0_DATA4~DATA19.

This connection is quite from the data bus connection used in

https://community.freescale.com/thread/314211

which is,

CSIx_DAT2 ~ CSIx_DAT9 <----> C[0] ~ C[7], CSIx_DAT12 ~ CSIx_DAT19 <----> Y[0] ~ Y[7].

I don't understand why this kind of connection is used.

And is it related to the setting of CCIR_CODE1/2/3 registers?

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139 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

For BT1120 mode capture, what we had verified is the 16bits mode, for CCIR code, it is correct in "https://community.freescale.com/thread/314211".

Your data line link is wrong "CSI0_DATA4 ~ DATA19".

For your case, IPU_CSI_SENS_CONF setting, for 16bits BT1120 input, CSI0_DATA_WIDTH should be 0001 8 bits per color; CSI0_SENS_DATA_FORMAT is 010 YUV422 (UYVY...); CSI0_SENS_PRTCL is 101 CCIR progressive (BT.1120 SDR mode: data arrives only on the positive edge of the clock).


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139 Views
allanmatthew
Contributor IV

Hi Qiang-

I'm also working on interfacing a 16-bit BT1120 input from an ADV7610.  I've previously been able to get the 8-bit BT656 version working, but the 16 bit is proving more difficult.

I've connected the pins as described in "https://community.freescale.com/thread/314211", however I'm not quite sure what to do with DATA0, DATA1, DATA 10 and DATA11.  Should they be pulled to ground or left floating?

The ADV7610 is configured for 16-bit SDR.  My CSI0_DATA_WIDTH is set to 0001, CSI0_SENS_DATA_FORMAT is 010, CSI0_SENS_PRTCL is 101 as you describe.  However, I get a mxc_v4l_dqueue timeout.

Is there any way to debug what CCIR codes the i.MX6 is reading in order to determine why the dqueue is not triggering?

-Allan

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139 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

Hi Allan, your CSI config register setting is OK. And CSI DATA0, 1, 10, 11 are not cared in this case.

But you must set the CCIR registers for the interlaced input, you can reference to BT656 code, it should be used for BT1120 mode too. If you are using other resolution, please update the width and height setting.

} else if ((cfg_param.clk_mode ==

   IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) ||

  (cfg_param.clk_mode ==

   IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) {

  if (width == 720 && height == 625) {

   /* PAL case */

   /*

    * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,

    * Field0ActiveEnd = 0x4, Field0ActiveStart = 0

    */

   __raw_writel(0x40596, CSI_CCIR_CODE_1(csi));

   /*

    * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,

    * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1

    */

   __raw_writel(0xD07DF, CSI_CCIR_CODE_2(csi));

   __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));

  } else if (width == 720 && height == 525) {

   /* NTSC case */

   /*

    * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,

    * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1

    */

   __raw_writel(0xD07DF, CSI_CCIR_CODE_1(csi));

   /*

    * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,

    * Field1ActiveEnd = 0x4, Field1ActiveStart = 0

    */

   __raw_writel(0x40596, CSI_CCIR_CODE_2(csi));

   __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi));

  } else {

   spin_unlock_irqrestore(&ipu_lock, lock_flags);

   dev_err(g_ipu_dev, "Unsupported CCIR1120 interlaced "

     "video mode\n");

   return -EINVAL;

  }

139 Views
allanmatthew
Contributor IV

Thanks Qiang-

I was able to get it up and running.  I used the interface described in "https://community.freescale.com/thread/314211" and used internal pulldowns to pull DATA0,1, 10 and 11 low.  Using the exisitng CCIR codes seemed to work as well.  Thanks!

-Allan

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139 Views
Pankh
Contributor I

Hi Allan,

We are planning to use ADV7611/ADV7610 with iMX6 processor.

Could you please share the linux device driver of ADV7610 for iMX6?

or

Could you please share the link or source where we can get the device driver of ADV7610 for iMX6

Regards,

Pankaj

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