Linux kernel provide some apis to allow changing dtb node after system booted. But the node change must happen before the driver loading. We can use gereral dtb file and add some dts node after system boot.

Q: What is the Min LPDDR2 clock frequency allowed by the i.MX6? The Jedec Spec for LPDDR2 allows for a min tck period of 100ns. Are there any required relashionship between the DDR clock frequency and other clocks in the i.MX6? A: The JEDEC maximum period for the MX6 is 100nS as per the LPDDR2 specification.  There is a minimum period during boot, before everything is configured and fully up to speed of 18nS. Are you saying the imx6 memory controller can operatate down to the min frequecies specified in the LPDDR2 JEDEC spec? Given that there is no limit specified in the data sheet, it should operate that slowly, provided the clocking can be set for it to operate so slowly. I would imagine that the core will need to be running slowly as well, since it does not make sense to slow the memory bus without slowing the core down as well.

Features Additional Information Features The i.MX31 PDK, with Smart Speed™ technology, is a completely integrated hardware and software solution that simplifies product development so you can focus on your critical differentiation needed for market success. Reduce development time, and design products that have power to spare, even when running multiple applications simultaneously. Receive stellar image and graphic performance in a system design that dramatically reduces power consumption. The i.MX31 PDK provides: Modular hardware enabling multiple connectivity technologies Optimized development software for Linux®, Windows® CE 5.0 and Windows Embedded CE 6.0 operating systems Out-of-box experience, complete with demonstration software and performance data Maximum performance and power savings Complete "Design. Debug. Demo." capability as simple as 1,2,3 i.MX31 Applications Processor Module i.MX31 Applications Processor - ARM11™ 128 MB DDR SDRAM 256 MB NAND FLASH Power Management (PMIC MC13783) + Power Circuitry Audio HS USB PHY Touch Controller Connector Debug Module (Software Development) Debug Ethernet Port Debug Serial Port JTAG Reset, Interrupt, Boot Switches Debug LEDs CodeTest Interface Power Source Current/Power Monitoring Personality Module (Demo-ready) Acceleromater MMA7450L (Freescale) User I/O Connectivity (FM, 802.11, Bluetooth, USB OTG, USB HS) Button 2.7"TFT Display 2MP Camera Module SDcard, ATA HDD External Connectors (dock, headphones, TV out, GPS) Microphone Speaker Additional Information i.MX31 PDK Contents If you are new to i.MX31PDK development we suggest checking out:Not authorized to view the specified document 1673 To flash BootLoader: i.MX31 PDK Board Flashing Miscellaneous Tutorials Blink i.MX 31PDK LEDs Using U-Boot i.MX31 Testing RNGA I.MX31 Testing TvOut I.MX31 Using CLKO

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-344473 

►How to Modify U-boot configure for change memory size to 512M •Only need change the u-boot memsize configure.      #define PHYS_SDRAM_1_SIZE                                                         (1u * 512 * 1024 * 1024) ► Use the performance tool Antutu test system in 512M and in 1024M.      * The statistic of Memory free after each test.     * The improve test is reduce GPU reserve physical memory size from 192M to 128M ► System boot-up reserve. (Static)     ► DMA allocate page and mem page.(Dynamic) ► Use for page alloc  < 292392K ► Browser speed     * The Browse speed in 512M is nearly with in 1024M ► Conclusion:   It is acceptable for this performance when use 512M physical memory.

In order to get Redboot running on i.MX35 PDK without a flashing procedure, a little modification in the binary file is needed. After that it can be loaded into RAM memory using the ATK tool. The Redboot Header To execute the binary Redboot file a header of 32 bytes long must be added: ddccbbaa0000000000000000hhggffee00000000000000000000000000000000 Where ddccbbaa is the 4-byte start address and hhggffee is the start address (all in Hexadecinal format) modified by the following procedure: value - 0x20 (or 32 decimal) + 0x08 (or 8 decimal) Note that in this header the values are placed from LSB to MSB bytes, so if the start address for MX35PDK is 0x87F00000 then the header should looks like: Start Address    --> 0x87F00000                                               --> 0000F087 Modified Address --> 0x87F00000 - 0x20 + 0x08 = 0x87EFFFE8 --> E8FFEF87 Header --> 0000F0870000000000000000E8FFEF8700000000000000000000000000000000 Now, this header must be appended to the beginning of the redboot.bin file.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-345148 

Features Additional Information Detailed Features List of i.MX31ADS board This is a development tool which is designed to run software applications designed for i.MX31 (MCIMX31) microprocessor unit (MPU). The MCIMX31ADS includes a baseboard, a CPU board, a power management board, an LCD display panel, a keypad, a NAND Flash card, an image sensor, etc. It supports application software, target-board debugging, or optional extra memory. Features Three board system Base board with display and interface connectors CPU board with i.MX31 ARM-11 MCU Power management board with MC13783 Atlas chip +5.0 VDC, 2.4 A universal power supply QVGA LCD display panel with touchscreen capability and LED backlight Keypad with 64 push button keys Image sensor camera Configurable intelligent management of system power Separate selectable voltage regulators for running the CPU board in stand-alone mode Two selectable system clock sources, 32.768 kHz and 26 MHz Onboard CPLD that manages memory-mapped expansion I/O, interrupts, and general-purpose I/O Multi-ICE debug support 32 MB of 16-bit NOR burst flash memory 16 MB of 16-bit PSRAM 128 MB of 32-bit DDR SDRAM memory Two sets of two memory card connectors, selectable as SD/MMC (on Base board) or MS (on CPU board), with card-sense functionality 1G-bit x8 data NOR Flash on a removable card SIMM card connector PCMCIA connector NAND Flash card connector Three RS-232 interfaces with DB-9 connectors driven by UART channels internal to the MX31. Each interface has two UART options and power up enable DIP switches. One supports DCE with optional full modem controls, another is DTE with optional full modem controls, and the third is DTE with RTS/CTS controls only. An external DUART configured as two RS-232 DCE channels (one DB9 connector, one 10-pin header) Two USB host transceivers, one full-speed and one high-speed, with standard USB host connectors Three USB OTG transceivers, one full-speed and one high-speed on the Base board, one full-speed on the Atlas board, with mini AB connectors 10 Base-T Ethernet controller with RJ-45 connector with built-in data flow LED indicators IrDA Specification 1.4 transceiver supports fast, medium, and slow operating modes ATA5 controller with 44-position dual row, 2 mm header for small form-factor disk drives I2C interface with one of two selectable MCU interfaces CSPI connector Two CSI connectors, with different image sensor orientations Smart serial LCD display connector QVGA LCD display connector with touch screen interface plus companion connector with additional control signals Two smart parallel LCD display connectors TV encoder connector Keypad connector Interface connector to baseband processor Audio synthesizer chip with microphone and line inputs (3.5 mm jacks); line, voice, and headphone outputs (3.5 mm jacks); and speaker output (screw terminals) Eight DIP configuration switches with user-definable functions Software-readable CPU and Base board versions LED indicators for +5V IN, 3.3V, vibrator output, and synthesizer output. Two LED indicators for user-defined function Piezoelectric audible alert and vibratory alert Three RGB funlight indicators and funlight connector Push button Reset (on CPU) or reset control from Atlas 1-wire EPROM • Push button interrupt source Two Mictor LA/SW Analysis Connectors (Base board) Four Samtec LA Connectors (CPU) Three Extension connectors, two are compatible with the MX21 ADS Extension connectors Special Atlas board features Stereo microphone jack, normal microphone jack, external TXIN jack, headphone jack, low level stereo input and output jacks, stereo and mono (ear piece) speaker terminals Main battery emulation from +5V Main battery connection terminals Back up battery emulation (super cap) Coin cell (backup) battery connection terminals Battery charger input terminals Backlight LED indicators Three Push button switches to act as power on/off switches DIP switches to select default power up power and power sequencing. USB mode, USB enable, and WDI disable DIP Switches. Audio clock source selection DIP Switches. Individual test point and LED indicator for each Atlas voltage USB cables, RS-232 serial cable, and two RJ-45 Ethernet cables, network, and crossover Additional Resources Booting Linux From NAND Flash on the i.MX 31 ADS IMX31ADS Compiling Linux kernel mainline

When boot from battery, then plug in 5V cable, the actual charging current can't reach the preset charging current. It is because the HEADROOM_ADJ is not correctly set. Please use attached mx28_chargingcurrent_limit_bootfrombattery.patch. Grace

i.MX31 Lite Kit is a low cost development board developed by LogicPD OEM (an AMD company). Expanding on the Freescale offering of low-cost, high-performance application development kits, Freescale introduces the i.MX31 Lite Kit. Developed in collaboration with Logic Product Development, the Freescale i.MX31 Lite Kit provides a product-ready software and hardware platform for OEMs, ODMs, IDHs and independent developers. The i.MX31 Lite Kit enables rapid design of embedded products targeting the medical, industrial, wireless, consumer markets and general purpose markets. Leverage the power of our popular i.MX 31 multimedia processor in this cost-effective development solution. Features The Freescale i.MX31 SOM-LV is based on the i.MX31 multimedia applications processor running up to 532 MHz. LCD Display Connector Integrated LCD, touch, and backlight connector for Zoom Display Kits Audio Stereo input and output jacks Network Support One RJ45 Ethernet jack connector with magnetics (application/debug) PC Card Expansion CompactFlash® Type I card MMC/SD card ATA Support USB One USB 2.0 high-speed host interface One USB high-speed On-the-Go device interface Serial Ports 115.2kbps RS-232 debug serial port Software LogicLoader™ (bootloader/monitor) Windows® CE 5.0 BSP GNU cross development toolchain (compiler, linker, assembler, debugger) Cables Serial cable (null-modem) Ethernet crossover cable USB A to mini-B cable 5 volt power supply (with Europe, Japan, UK, & US adapters) Mechanical 146.1 mm wide x 158.8 mm long x 17.1 mm high RoHS Compliant More information [here.]

Creating Deployment System          Configuring Bootloader       Running Linux     

Computer On Module • Processor Freescale i.MX535,1GHz/i.MX536, 800MHz • RAM 512MB/1GB DDR3 SDRAM • ROM 4GB EMMC,up to 32GB • Power supply Single 3.1V to 5.5V • Size 54mm SO-DIMM • Temp.-Range -20°C..70°C   -40°C..120°C Key Features • 10/100Mbps Ethernet • Two High Speed USB 2.0 ports • LCD controller up to 1600 x 1200, 24bpp • OpenGL ES 2.0 and OpenVG 1.1 hardware accelerators • Multi-format HD 1080p video decoder and 720p video encoder hardware engine • Two Camera Interfaces • NEON SIMD media accelerator • Unified 256KB L2 cache • Vector Floating Point Unit • Several interfaces: 3x UART, 2x SDIO, 2x SSI/AC97/I2S, I2C, CSPI, Keypad, Ext. Memory I/F • 3.3V I/O OS Support     • Linux     • Android Application:Smart mobile devices,Smart Display,Automotive Infotainment,Digital Signage, Telemedicine,Retail POS Terminal,Security,Barcode Scanner,Visual IP Phone,Patient Monitors,Surveillance Cameras,building control, factory / home automation, HMI For more information, please see Attachment We can provide a complete solution

    Attached is the SDHC DMA read supported patch, it is based on WCE600_MX51_ER_1104, it was verified on iMX51 EVK board. The SDHC DMA read can reduce the NK copy time, in this way it can speed up the WinCE boot.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343017 

I followed the Yocto Training up until Task #4 - Deploy and test.... and I got stuck here. I am not able to download the .sdcard image to my SD card. Do I need to format it first? It is brand new. Since the sudo dd if=core-image-base-imx6solosabresd.sdcard of=/dev/sdb1 bs=1M did not work for me, I was not able to boot from the SD on my board. The board switches are set to boot from SD4. Is imx6solosabresd the correct MACHINE to use for the solox? I tried setting MACHINE=imx6sxsabersd in the local.conf file but I got an error message (Task #2). This is why I want to try the MFGTool. I have set the board to boot from SD3 so it can go into "download mode". When I go through the MFGTool, it says No Device Connected although HID-compliant vendor-defined device shows up. This document was generated from the following discussion: 

 

An i.MX50 customer encountered such kernel bug recently. Android UI has no response, because the suspend work queue is blocked:     suspend       pm_suspend         enter_state           suspend_prepare / suspend_finish             pm_prepare_console / pm_restore_console               vt_move_to_console                 vt_waitactive                   vt_event_wait                     wait_event_interruptible Confimed the same bug can also happen on imx6SL which is running linux 3.0.35. e.g. by echo standby/mem > /sys/power/state It takes over thousand suspend/resume cycles to reproduce the problem. The bug fix has been merged since linux 3.6: commit a7b12929be6cc55eab2dac3330fa9f5984e12dda

Please join us for a webinar tomorrow - July 30 at 10 AM CDT. Register here: https://info.cranksoftware.com/resources/modernize-embedded-graphics-ultra-low-power-ui-nxpcranksoftware NXP’s i.MX 7ULP applications processor, alongside Crank's Storyboard GUI design and development software, gives embedded teams the best of both worlds – rich 2D/3D performance with MCU-level low power. Join Brian Edmond and Nik Jedrzejewski to get a technical deep dive into the i.MX 7ULP and Storyboard and learn: the latest trends in graphics for battery-powered devices hardware features of the i.MX 7ULP, including the Heterogeneous Domain Computing architecture how to leverage Storyboard's hybrid rendering solution when switching between 2D and 3D graphics to minimize power consumption   PANELLISTS Brian Edmond, President, Crank Software Nik Jedrzejewski, i.MX Product Manager, NXP

 

You can power on/off i.MX31 PDK LEDs using U-Boot: u-boot> mw.b B6020000 FF Where B6020000 is the CPLD LED address and FF is the 8 bits hexadecimal value which will be displayed on LEDs.