Current the SSI is set to I2S slave mode in FSL default release BSP. attached the code for how to set it to master mode.

Features Additional Information Detailed Features List of i.MX31ADS board This is a development tool which is designed to run software applications designed for i.MX31 (MCIMX31) microprocessor unit (MPU). The MCIMX31ADS includes a baseboard, a CPU board, a power management board, an LCD display panel, a keypad, a NAND Flash card, an image sensor, etc. It supports application software, target-board debugging, or optional extra memory. Features Three board system Base board with display and interface connectors CPU board with i.MX31 ARM-11 MCU Power management board with MC13783 Atlas chip +5.0 VDC, 2.4 A universal power supply QVGA LCD display panel with touchscreen capability and LED backlight Keypad with 64 push button keys Image sensor camera Configurable intelligent management of system power Separate selectable voltage regulators for running the CPU board in stand-alone mode Two selectable system clock sources, 32.768 kHz and 26 MHz Onboard CPLD that manages memory-mapped expansion I/O, interrupts, and general-purpose I/O Multi-ICE debug support 32 MB of 16-bit NOR burst flash memory 16 MB of 16-bit PSRAM 128 MB of 32-bit DDR SDRAM memory Two sets of two memory card connectors, selectable as SD/MMC (on Base board) or MS (on CPU board), with card-sense functionality 1G-bit x8 data NOR Flash on a removable card SIMM card connector PCMCIA connector NAND Flash card connector Three RS-232 interfaces with DB-9 connectors driven by UART channels internal to the MX31. Each interface has two UART options and power up enable DIP switches. One supports DCE with optional full modem controls, another is DTE with optional full modem controls, and the third is DTE with RTS/CTS controls only. An external DUART configured as two RS-232 DCE channels (one DB9 connector, one 10-pin header) Two USB host transceivers, one full-speed and one high-speed, with standard USB host connectors Three USB OTG transceivers, one full-speed and one high-speed on the Base board, one full-speed on the Atlas board, with mini AB connectors 10 Base-T Ethernet controller with RJ-45 connector with built-in data flow LED indicators IrDA Specification 1.4 transceiver supports fast, medium, and slow operating modes ATA5 controller with 44-position dual row, 2 mm header for small form-factor disk drives I2C interface with one of two selectable MCU interfaces CSPI connector Two CSI connectors, with different image sensor orientations Smart serial LCD display connector QVGA LCD display connector with touch screen interface plus companion connector with additional control signals Two smart parallel LCD display connectors TV encoder connector Keypad connector Interface connector to baseband processor Audio synthesizer chip with microphone and line inputs (3.5 mm jacks); line, voice, and headphone outputs (3.5 mm jacks); and speaker output (screw terminals) Eight DIP configuration switches with user-definable functions Software-readable CPU and Base board versions LED indicators for +5V IN, 3.3V, vibrator output, and synthesizer output. Two LED indicators for user-defined function Piezoelectric audible alert and vibratory alert Three RGB funlight indicators and funlight connector Push button Reset (on CPU) or reset control from Atlas 1-wire EPROM • Push button interrupt source Two Mictor LA/SW Analysis Connectors (Base board) Four Samtec LA Connectors (CPU) Three Extension connectors, two are compatible with the MX21 ADS Extension connectors Special Atlas board features Stereo microphone jack, normal microphone jack, external TXIN jack, headphone jack, low level stereo input and output jacks, stereo and mono (ear piece) speaker terminals Main battery emulation from +5V Main battery connection terminals Back up battery emulation (super cap) Coin cell (backup) battery connection terminals Battery charger input terminals Backlight LED indicators Three Push button switches to act as power on/off switches DIP switches to select default power up power and power sequencing. USB mode, USB enable, and WDI disable DIP Switches. Audio clock source selection DIP Switches. Individual test point and LED indicator for each Atlas voltage USB cables, RS-232 serial cable, and two RJ-45 Ethernet cables, network, and crossover Additional Resources Booting Linux From NAND Flash on the i.MX 31 ADS IMX31ADS Compiling Linux kernel mainline

When boot from battery, then plug in 5V cable, the actual charging current can't reach the preset charging current. It is because the HEADROOM_ADJ is not correctly set. Please use attached mx28_chargingcurrent_limit_bootfrombattery.patch. Grace

Unpack the kit Boards CPU board Debug board Personality board Cables RS-232 serial cable Ethernet straight cable High-speed USB cables with mini AB connectors for OTG High-speed cable with standard A to mini B connectors Mini-USB adaptor Jack to RCA audio/video cable Power Supply 5.0V/2.4A universal power supply kit Paperwork CD-ROMs: Content CD End-User License Agreement Quick Start Guide (this document) Warranty card Freescale Support card Build the platform Connect the Personality board to Debug board. The personality board connects to the Debug board using a 500-pin connector. The connector is keyed to avoid misconnection, so there is only one way to connect these boards. Then, connect the CPU board to the underside of Debug board. Certify the version of bootloader When updating the BSP files of a system, it's recommended to rewrite a right version of bootloader in the target. Connect platform to PC To connect the 3-Stack platform to your host PC: Connect one end of an RS-232 serial cable (included in the kit) to a serial port connector (CON4) on the Debug board and connect the other end to a COM port on the host PC. Configure SW4-1 to ON. Make sure that SW4-8 is ON, to supply power to all three boards. Configure SW4-2 to OFF. Confirm that the Bootstrap switches (SW5–SW10) are set for external NAND boot (see more here) Connect the regulated 5V power supply to the appropriate power adapter. Plug the power adapter into an electrical outlet and the 5V line connector into the J2 (5V POWER JACK) connector on the Debug board. Start a serial console application on your host PC with the following configuration: Baud Rate 115200 Data Bits 8 Parity None Stop Bits 1 Flow Control None On the Debug board, switch the power switch (S4) to 1. The OS image pre-loaded in the 3-Stack board will boot and the debug messages from the bootloader should now appear on the serial console application on your PC See Also For a setting without the Debug board see Demonstration Platform.

You can power on/off i.MX31 PDK LEDs using U-Boot: u-boot> mw.b B6020000 FF Where B6020000 is the CPLD LED address and FF is the 8 bits hexadecimal value which will be displayed on LEDs.

Please join us for a webinar tomorrow - July 30 at 10 AM CDT. Register here: https://info.cranksoftware.com/resources/modernize-embedded-graphics-ultra-low-power-ui-nxpcranksoftware NXP’s i.MX 7ULP applications processor, alongside Crank's Storyboard GUI design and development software, gives embedded teams the best of both worlds – rich 2D/3D performance with MCU-level low power. Join Brian Edmond and Nik Jedrzejewski to get a technical deep dive into the i.MX 7ULP and Storyboard and learn: the latest trends in graphics for battery-powered devices hardware features of the i.MX 7ULP, including the Heterogeneous Domain Computing architecture how to leverage Storyboard's hybrid rendering solution when switching between 2D and 3D graphics to minimize power consumption   PANELLISTS Brian Edmond, President, Crank Software Nik Jedrzejewski, i.MX Product Manager, NXP

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343017 

Created by prathamrahate  For loading u-boot using JTAG, follow the below steps-- 1. Download DDR stress test tool v.2.52 from NXP website. 2. Boot your board into serial mode, by turning all boot switches off 3. Now connect USB cable from USB OTG port to desktop/Laptop on which you will be running DDR stress test tool. 4. For information on using DDR stress test tool refer to documentation. 5. Once board is detected in DDR stress test tool, use appropriate inc script in the tool and click on download. After successful downloading of script , DDR will be initialised. 6. Now connect JTAG cable , and load u-boot.bin image using load_image command from JTAG to appropriate address, for imx6q sabresd board it is 0x17800000. 7. Once image is downloaded successfully, you can resume from same address using resume command like resume 0x178000000 For custom boards, you can use xls provided by NXP to generate inc file for custom board which can be used for loading into DDR stress test tool to initalise DDR. I am using Arm olimex JTAG debugger for debugging. This document was generated from the following discussion: Loading u-boot.bin unsing JTAG on imx6q-sabresd board

This tutorial guides on setting up and running the NFC Demo App using the PN7120 NFC Click board with the i.MX 7Dual SABRE-SD and its mikroBUS socket compatible: MikroE NFC Click Board on i.MX7D - i.MXDev Blog

Fixing Redboot RAM bug (CSD1 not activated) Introduction i.MX 35 PDK board has 256 MB of RAM, due to a bug in Redboot bootloader compiled for the board effectively there is only 128 MB available.This procedure fixes this bug to be able to use 256 MB of RAM. Redboot supporting 256 MB of RAM 1. Download the attached Redboot256.bin file. 2. Flash the new redboot image instead of the old one: Configuring RedBoot

i.MX31 Lite Kit is a low cost development board developed by LogicPD OEM (an AMD company). Expanding on the Freescale offering of low-cost, high-performance application development kits, Freescale introduces the i.MX31 Lite Kit. Developed in collaboration with Logic Product Development, the Freescale i.MX31 Lite Kit provides a product-ready software and hardware platform for OEMs, ODMs, IDHs and independent developers. The i.MX31 Lite Kit enables rapid design of embedded products targeting the medical, industrial, wireless, consumer markets and general purpose markets. Leverage the power of our popular i.MX 31 multimedia processor in this cost-effective development solution. Features The Freescale i.MX31 SOM-LV is based on the i.MX31 multimedia applications processor running up to 532 MHz. LCD Display Connector Integrated LCD, touch, and backlight connector for Zoom Display Kits Audio Stereo input and output jacks Network Support One RJ45 Ethernet jack connector with magnetics (application/debug) PC Card Expansion CompactFlash® Type I card MMC/SD card ATA Support USB One USB 2.0 high-speed host interface One USB high-speed On-the-Go device interface Serial Ports 115.2kbps RS-232 debug serial port Software LogicLoader™ (bootloader/monitor) Windows® CE 5.0 BSP GNU cross development toolchain (compiler, linker, assembler, debugger) Cables Serial cable (null-modem) Ethernet crossover cable USB A to mini-B cable 5 volt power supply (with Europe, Japan, UK, & US adapters) Mechanical 146.1 mm wide x 158.8 mm long x 17.1 mm high RoHS Compliant More information [here.]

Related links: i.MX Power Profiling System: Smart Current Sensor and Aggregator Shield  i.MX Power Profiling System: Aggregator Shield Details   i.MX Power Profiling: Triple-range Smart Current Sensor   Examples of boards instrumented with Smart Sensors. (Some close-ups will be added later.) One rail of the i.MX7ULP SOM is instrumented here. The sensor is immobilized with foam double sticky tape on top of the i.MX7ULP (trying to minimize contact to just that so the tape is more easily removed later). Immobilization is necessary in order to prevent ripping the resistor pads off the target board. The series resistor on the board is removed and the smart sensor is wired into place. Note here that the sensor is shorted so that the SOM will operate while the Smart Sensor being unpowered. The Smart Sensors MUST be powered via the Aggregator in order for the target board to operate. Otherwise, the target board will be starved of power and it will not operate unless all of the Smart Sensors connected to it are powered. An unpowered Smart Sensor presents an open circuit between the input and output terminals. Here are nine rails instrumented on the i.MX8QM CQC board. One rail Smart Sensor is in the bottom side, the rest are all on top. There is one double sticky taped to the back of the connectors at the back of the photo (the SCU supply, relatively low current, which can tolerate longer wires/series resistance). The rest are connected with 24 gauge wire, no longer than about half an inch long, to keep the series resistance low. The ground wire (center contact) can be a 30 gauge wire-wrap wire, which was used for all the grounds here. Note that the stiff connection wires allow the sensors to stand up in place, which is very helpful since there is no room to double sticky tape the sensors down. This board was not laid out with instrumentation in mind. Here is an i.MX8QXP CQC board with four rails instrumented. Two of the sensors are on top and two on the the bottom. They are not double sticky taped into place, but they are shielded with heat shrink tubing to prevent any contact with the target board. As above, 24 gauge wires are used for the current in/out lines, 30 gauge wire is used for all the ground contacts. Out of the frame, the four ribbon cables are bundled together to prevent the wires and sensors from moving too much. As above, the heavy wires have been kept as short as possible.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-341570 

This is done with the 11.09 BSP for imx53 specifically. Attached is an amrnb.spec file, I put it in ltib/dist/lfs-5.1/amrnb. Then I extracted opencore-amr-0.1.3.tar.gz and put it in ltib/rpm/BUILD. I built with ltib ( ALl this could be added to the ltib menus as well 😞 ./ltib –m scbuild –p amrnb ./ltib –m scdeploy –p amrnb Then I applied the patch to .ltib for gst-plugins-ugly and built that with ltib. It will play a .3gp file with this pipeline: gst-launch filesrc location=/media/sd/test.3gp ! qtdemux name=demux demux.audio_00 ! queue ! amrnbdec ! alsasink demux.video_00 ! multiqueue ! mfw_vpudecoder ! mfw_isink Regards, Randy Krakora

This table shows how to configure i.MX51 EVK DIP Switches to boot from SD card and how to boot from internal ROM to use ATK: DS1 DS2 DS3 DS4 DS5 DS5 DS7 DS8 DS9 DS10 Boot from SD/MMC Card 0 0 0 0 0 0 1 1 0 0 Boot from i.ROM (ATK) 1 1 0 0 0 0 1 1 0 1

From iMX 3.1x kernel, all kernel debug messages will be print to debug serial port after UART driver loaded, so if the kernel hang up before tty console driver ready, there will be no kernel boot up messages.   The attached patch can be used to enable the iMX serial debug console in early time, then kernel will not buffer the debug messages.   Note: the default patch is for UART1 (tty0) as the debug port, if you need use other debug port, please modify the code "early_console_setup()" with correct UART port base address.   L3.10.53-Add-early-console-for-debug-message.patch This patch is based on L3.10.53_GA1.1.0 release, it can support iMX6S/DL/D/Q.   L3.14.52-Add-early-console-for-debug-message.patch This patch is based on L3.14.52_GA1.1.0 release, it can support iMX6S/DL/D/Q, iMX6SL, iMX6SX, iMX6UL and iMX7.  

Platform: i.MX8MP EVK BSP: Linux 5.4.70.2.3.0 Customer reported UI on HDMI monitor is abnormal and has more line on left side when doing HDMI hot-plug on i.MX8MP running with L5.4.70.2.3.0.   This issue can’t be reproduced on latest BSP such as 5.10 and above, several patch for HDMI from latest BSP can fix this issue.  

- In LTIB generate a rootfs.jffs2 with a erase block size of 16KB: ./ltib -c ---Target Image Generation   Options ---> ---Choose your root file system image type     Target image: (jffs2) --->   (16) jffs2 erase block size in KB - Copy the generated rootfs.jffs2 to /tftpboot : cp rootfs.jffs2 /tftpboot - Program 200732 Redboot binary. The 200732 Redboot is available in the 20071008 BSP iso. After mounting the iso go to the bootloaders directory, extract the redboot_200732.tar.gz file and use the pre-built mx31ads_redboot.bin inside the bin directory. - Boot from NAND and setup the network parameters fis init load -r -b 0x100000 /tftpboot/zImage fis create -l 0x200000 kernel load -r -b 0x100000 /tftpboot/rootfs.jffs2 fis create -l 0x1d000000 root - Pass the following kernel command line: fis load kernel exec -b 0x100000 -l 0x200000 -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock6 rootfstype=jffs2 init=linuxrc ip=none mtdparts=mx" You need to replace mtdblock6 with your rootfs partition, see below: mx31# cat /proc/mtd dev:    size  erasesize  name mtd0: 00040000 00020000 "RedBoot" mtd1: 001a0000 00020000 "kernel" mtd2: 0001f000 00008000 "FIS directory" mtd3: 00001000 00008000 "RedBoot config" mtd4: 00040000 00004000 "RedBoot" mtd5: 00200000 00004000 "kernel" mtd6: 01d00000 00004000 "root" mtd7: 00003000 00004000 "FIS directory" mtd8: 00001000 00004000 "RedBoot config" mx31#

i.MX 6 SoloX MCC MCC is a library for lightweight communication between cores Configured at compile time (mcc_config.h) Current version (2.0) is not backward compatible MCC works with shared memory area Communication is performed through ‘send’ and ‘receive’ functions Shared memory Cores communicate through shared memory Core structures of the MCC  MCC_ENDPOINT core Identifies a processor core, A9 is 0 and M4 is 1. node In Linux, each process using MCC has its own node number. MQX has only one node number. port Any number of ports per node is allowed. Value MCC_RESERVED_PORT_NUMBER is not allowed. The number of endpoints in system is defined during compile time by macro MCC_ATTR_MAX_RECEIVE_ENDPOINTS. MCC_BOOKEEPING_STRUCT Endpoint table I. MCC API  Functions Standard API −int mcc_initialize(MCC_NODE); −int mcc_destroy(MCC_NODE); −int mcc_create_endpoint(MCC_ENDPOINT*, MCC_PORT); −int mcc_destroy_endpoint(MCC_ENDPOINT*); −int mcc_send(MCC_ENDPOINT*, MCC_ENDPOINT*, void*, MCC_MEM_SIZE, unsigned int); −int mcc_recv(MCC_ENDPOINT*, MCC_ENDPOINT*, void*, MCC_MEM_SIZE, MCC_MEM_SIZE*, unsigned int); −int mcc_msgs_available(MCC_ENDPOINT*, unsigned int*); −int mcc_get_info(MCC_NODE, MCC_INFO_STRUCT*); MCC_SEND_RECV_NOCOPY_API_ENABLED −int mcc_get_buffer(void**, MCC_MEM_SIZE*, unsigned int); −int mcc_send_nocopy(MCC_ENDPOINT*, MCC_ENDPOINT*, void*, MCC_MEM_SIZE); −int mcc_recv_nocopy(MCC_ENDPOINT*, MCC_ENDPOINT*, void**, MCC_MEM_SIZE*, unsigned int); −int mcc_free_buffer(void*);