Low power demo on i.MX8MM.
9/28/2020:
Attachments updated.
1. Fix a bug in 5.4.24 kernel that system can only wakeup once.
2. Remove 0x104 from atf patch. On 5.4.24, tested OK without PLL2.
9/8/2020:
Attachments updated.
Add patches for 5.4.24 kernel.
We use it to test power consumption on i.MX8MM EVK.
Usage:
1. Kernel:
echo "mem" > /sys/power/state
2. M4:
Select a power mode from menu and wait for wakeup.
Default wakeup method is GPT.
Add more patches, which will add functions for the case:
1. M core RUN and A core in suspend with DDR OFF.
2. M core wakeup A core without DDR support.
Descriptions:
freertos_lowpower.zip. A simple freertos example for M4 RUN when A core in DSM. Generally, we use MU_TriggerInterrupts(MUB, kMU_GenInt0InterruptTrigger); to do wakeup.
low_power_demo.zip A simple baremetal example for M4 RUN when A core in DSM. Generally, we use MU_TriggerInterrupts(MUB, kMU_GenInt0InterruptTrigger); to do wakeup. Note that the freertos version will have more options in menu.
atf patch: Allow A53 to enter fast-wakeup stop when M4 RUN. Also avoid bypass of some plls, which is important to make M4 RUN when A53 enters suspend.
0001-iMX8MM-GIR-wakeup.patch: GIR wakeup patch for kernel. Need kernel to use fsl-imx8mm-evk-m4.dtb.
0002-Don-t-keep-root-clks-when-M4-is-ON.patch. Don't keep root clocks when M4 is ON.
0001-plat-imx8mm-keep-the-necessary-clock-enabled-for-rdc.patch. There's a design issue that when wakeup from DSM, described in patch: "if NOC power down is enabled in DSM mode, when system resume
back, RDC need to reload the memory regions config into the MRCs, so PCIE, DDR, GPU bus related clock must on to make sure RDC MRCs can be successfully reloaded." Note that this patch will keep PCIE, DDR and GPU clock on, which will increase the power. An optimization will be decrease PCIE, DDR and GPU clock before entering DSM.
Power measurement:
Supply Domain
Voltage(V)
I(mA)
P(mW)
peak
avg
peak
avg
peak
avg
VDD_ARM(L6)
1.010029
1.009513
1.109
1.030
1.120
1.039
VDD_SOC(L5)
0.855199
0.854857
190.110
189.973
162.582
162.400
VDD_GPU_VPU_DRAM(L10)
0.977240
0.977050
19.865
19.800
19.413
19.346
NVCC_DRAM(L15)
1.094407
1.094168
2.059
1.984
2.253
2.171
Total
185.367
184.956
Notes:
This power measurements is got by putting Cortex-A in DSM and Cortex-M in RUNNING.
In other tests, if M core can be put to STOP mode, additional power can be saved (5 - 20mA in VDD_SOC).
From the table, we can see that by putting DDR to retain, a lot of power can be saved in VDD_SOC and NVCC_DRAM.
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