This is a tool can generate a LPDDR2 script easily for i.Mx6DQSDL and only need input several parameters based on using DDR datasheet and system architecture.
Please find more aids and tool through below links.
i.MX6DQSDL DDR3 Script Aid
i.MX6SL LPDDR2 Script Aid
i.MX6SX DDR3 Script Aid
I.MX6UL DDR3 Script Aid
i.MX6 DDR Stress Test Tool V1.0.3
Any questions are welcome!
version 0.02 -- Add CA calibration Tool link; Fix memory size error.
version 0.03 -- Fix memory size error.
version 0.04 -- Fix ZQ calibration risk
version 0.05 --
1. Support 512Mb density
2. remove config 0x020c4084
3. add DDR_PHY_P1_MPZQHWCTRL
version 0.06 --1. Change tXPR and SDE_to_RST to default value.2. Change MDOTC to default value.3. Reduce LPDDR2 support to 400 MHz4. add precharge all command before MRW reset
in the version 0.01 of the LPDDR2 scipt aid for the i.MX6 there are some problems that need to be fixed:
1) It should be made clear that this is about Bank Interleaving - not just call it "interleve" ;-)
2) when interleaving is activated the BI_ON bit in the MDMISC register should be set
3) in line 170 the comment is not preceeded by "//"
Could you please fix this and release an updated version asap?
Finally it would be nice to include also smaller memory sizes than 1Gb.
Please find updated Mx6DQSDL LPDDR2 Script Aid V0.02.xlsx
it would be nice if there will be a version where you insert all the timings like tRFC, tCL, tRAS and so on and you get the correct register values...
we are trying to configure our memory to the imx6 and we are progressing relative slowly due to being unsure about register values...
All timing parameters are aligned with JESD209-2.
If you are not sure, please refer to it.
According to reference manual for IMX6DL the DDR_SEL field of IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET should be set to LPDDR2, but in the script aid this is set to a reserved value. Which one is correct?
You can find all FSL released setting is same with aid at this point.
I have checked with design team before and it is internal calibration tune bit, current official released RM don't show detailed info about it.
So please follow aid and official released script setting.
Could you give some more information on why it should be set to the reserved value, and what it does? Since we're seeing improvements on our board when not using the reserved value (according to script aid) but instead following RM and setting it to LPDDR2. We're having problems running memory at 400MHz on our board, but when setting DRAM_RESET to LPDDR2 errors on address lines seems to go away. Although there's still problems with bit-flips for us for some reason, so it does not solve everything.
I'm running tests with memtester (memtester version 4) ported to u-boot and the first test "stuck address" reports errors when DRAM_RESET is set to the reserved bit.
As I know, it is tuned result by SOC designer and the RM will be updated in next release.
For your issue, it may not simple only related with that register and I suggest to ask local FAE's help first.
Are there any guides to port these settings to a board cfg for uboot? Or alternatively I wanted to copy the sheet and make a compatible uboot cfg file but noticed that all of the settings are password protected... whats the password?
You can configure uboot by following aid include value and sequence.
Ctrl+C is permitted.
Ok, that works, although i think there is something wrong with my settings. why is the document password protected? I'd like to copy the sheet so i can edit it and generate a uboot config. Copying and pasting works perfectly except each time I do it I have to find and replace setmem /32 and replace with DATA 4, as well as delete all the = characters.
Nvm, for some reason libre office wasn't letting me unlock the sheets even after copying, went to excel and right clicked on the sheet and was able to uncheck it. I now have a script that can be generated for uboot
I'm a greenhand,I want to know where to get the info how to use the i.Mx6DQSDL LPDDR2 Script Aid?
Sorry, I have no such guide for LPDDR2.
But you can refer to guide for DDR3.
You can find the link of guide in DDR3 aid page.
Hope that can help you!
If we using Dual channel LPDDR2.
DDR Memory Map Config[1:0] fuse value is set "00" or "01" or "10" ?
Both "01" and "10" are supported.
But I had test "00" , it can work. (We had change some U-boot setting base on 2x32 memory mapping.
If we set to "10" , MFG u-boot.bin can't boot up.
Is Document issue or not ?
This configuration should be done at boot config pin or Fuse.
Please refer to boot chapter in RM.
Where can we find "DDR_CA_Calibration_Vx.x.x"?
Please ask tool owner help through following page:
Or asking local FAE for help.
Thank you for your reply and will looking for FAE to help.
The link doesn't work...
Please try this update version.
i.MX6/7 DDR Stress Test Tool V2.10
V0.04 of this LPDDR2 Register Programming aid needs to be updated.
We found out that it is necessary to program register DDR_PHY_P1_MPZQHWCTRL for 2 channel operation. The following line should be added just after the line that programs register DDR_PHY_P0_MPZQHWCTRL:
setmem /32 0x021b4800 = 0xA1380003 // DDR_PHY_P1_MPZQHWCTRL
Could you please provider the password of the Mx6DQSDL LPDDR2 Script Aid V0.06.xlsx?
The Mx6DQSDL LPDDR2 Script Aid V0.06.xlsx version of the register programming aid is provided in a "locked" state for ease of customer use, so that customers do not accidentally change a parameter they should not be touching.
NXP does have more complex register programming aids available which allows customer to see and touch all of the registers. It is recommended that you have a good working knowledge of the MMDC chapter in the Reference Manual to use these aids. These can be found at...