i.MX6SX DDR3 Script Aid

cancel
Showing results for 
Search instead for 
Did you mean: 

i.MX6SX DDR3 Script Aid

No ratings

i.MX6SX DDR3 Script Aid

Note, the tools described in this page are deprecated and are no longer maintained.  For the latest maintained i.MX 6/7 series DDR tools, the user can find these here:

i.MX 6/7 Series DDR Tool Release

This is a tool can generate a DDR3 script easily for i.Mx6SX and only need input several parameters based on using DDR datasheet and system architecture.

Following docs(English or Chinese version) are also can be referred as a hand on guide.

Freescale i.MX6 DRAM Port Application Guide-DDR3

飞思卡尔i.MX6平台DRAM接口高阶应用指导-DDR3篇

 

Please find i.Mx6DQSDL DDR3 Script Aid through below link.

i.Mx6DQSDL DDR3 Script Aid

 

Please find i.Mx6DQSDL LPDDR2 Script Aid through below link.

i.Mx6DQSDL LPDDR2 Script Aid

 

Please find i.Mx6SL LPDDR2 Script Aid through below link.

i.MX6SL LPDDR2 Script Aid

 

Please find i.Mx6UL DDR3 Script Aid through below link.

I.MX6UL DDR3 Script Aid

 

Please find I.MX53 DDR3 Script Aid through below link.

I.MX53 DDR3 Script Aid

 

i.MX6 DDR Stress Test Tool

https://community.freescale.com/docs/DOC-96412

 

Any questions are welcome!

Attachments
Comments

Hi LinWang,

see below from SX tool . Can this be correct - Tool sets bits to "Reserved" rather than "DDR3".

DDR Select Field
Select one out of next values for pad: DRAM_RESET.
00 Reserved
01 Reserved
10 LPDDR2 mode (240Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at
1.2V)
11 DDR3 mode (240Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V
Recommend to set this to '00' per design

Hi Rooney,

I believe it is doc issue, will ask doc team correct it.

Please refer to i.MX6DQ RM, the correct info can be found.

Thanks for your digging it out.

LPs

Hi,

I want to init a 1866 DDR3 DRAM. There is an updated script that manage that kind of chips?

Or better could you give us the password to unlock formulas to make us able to correct it?

You can refer to following aid.

i.MX6SX DDR3 Register Programming Aid

Hi LinWang,

The script sets the DDR_INPUT bit = 1 in the register IOMUXC_SW_PAD_CTL_GRP_DDRMODE, which means "Differential input mode" for all of the DRAM_DATA signals.  These signals are all single-ended.

setmem /32  0x020e0608 = 0x0002000  // IOMUXC_SW_PAD_CTL_GRP_DDRMODE

Should this be set for single-ended, or is there an advantage to setting the DRAM_DATA pads to differential input mode?

Does it have an effect on timing?

Hello Norman,

This register configure internal circuit, there are two modes for IO comparation circuit.

Version history
Revision #:
2 of 2
Last update:
‎05-06-2021 01:07 PM
Updated by: