i.MX 6/7 Series DDR Tool Release
This is a tool can generate a DDR3 script easily for i.Mx6DQSDL and only need input several parameters based on using DDR datasheet and system architecture.
Following docs(English or Chinese version) are also can be referred as a hand on guide.
Freescale i.MX6 DRAM Port Application Guide-DDR3
Please find i.Mx6DQP DDR3 Script Aid through below link.
MX6DQP DDR3 Script Aid
Please find i.Mx6DQSDL LPDDR2 Script Aid through below link.
i.Mx6DQSDL LPDDR2 Script Aid
Please find i.Mx6SL LPDDR2 Script Aid through below link.
i.MX6SL LPDDR2 Script Aid
Please find i.MX6SX DDR3 Script Aid through below link.
i.MX6SX DDR3 Script Aid
Please find I.MX53 DDR3 Script Aid through below link.
I.MX53 DDR3 Script Aid
i.MX6 DDR Stress Test Tool
Any questions are welcome!
0.11 updateadd note for duty cycle consideration.
Do you think you could add a tab to automatically also set up the DS-5 "*.ds" file version format as well? I think it would be rather straightforward and very helpful.
Would you please share one sample file with me? Through email will be fine.
It is better the file with same configuration of "*.inc"
so far DDR stress test looks no power down test?!
is that possible to add in precharge power down test in DDR Stress Test?
Please go to stress test tool page https://community.freescale.com/docs/DOC-96412
and ask help.
The latest v0.10 with DS-5 script included, FYI.
I'm a little confused about the values in the SI Configuration section at the bottom of the Register Configuration tab of this script aid. Some of the lines are a mix of single ended and differential pairs, which should have different impedance's. However, they are grouped together and given a single number. More over, the iMX6 Hardware Development Guide section 3.3 recommends 50/100 ohms for single-ended/differential-pairs, however neither of those two numbers appear in the drop down boxes.
Am I missing something? Our boards are booting but completely failing the DDR3 Stress test, so any help or insights that anyone has would be appreciated.
I try to answer your question in Aid here.
Please refer to i.MX6 RM, you can find same DSE configuration value for signal and differential signals.
Both two signal pair have 50ohm output impedance then we can see 100ohm differential impedance.
Hope above info can help you!
For you board issue, please contact local FAE for help!
Does any DDR3 / LPDDR2 script for i.MX6 SoloX CPU ?
Don't have now.
has anyone used this on MX6 SoloX CPU yet ?
It will work I guess ??
This Aid can't not support MX6SX directly.
can you please update it to support SX part ?
Sure, I will.
But it will be ready next month.
Will update link in this page.
Please bookmake this page and then you can get notification.
LinWang, it shouldn't take so long.
The SX was unveiled in March but there is little or no support for it on the Freescale Website e.g. the IMX6 SDK does not support it ?
You may get support form local FAE.
BTW, I will speed up to release it.
Do you have a script for imx6DL DDR3?
Sure, all chips which follow JESD79-3D/F can use this aid.
Using the Script Aid V0.10 for an i.MX6DualLite, I found a bug in the worksheet: the setmem for DDR_PHY_P1_MPODTCTRL is enabled not only for 64-bit bus width, which is correct, but also for 16-bit bus width, which is incorrect and results in an "ERROR: DCD addr is out of valid range" failure in the Stress Test tool.
The fix to this bug is to change the test in the formula in A176, from "=32" to "<>64".
Hope this helps,
Which stress test tool version you are using?
And I can't udnerstand "The fix to this bug is to change the test in the formula in A176, from "=32" to "<>64"."
Would you please provide detailed description?
The stress test tool version is 2.40 (and Script Aid V0.10 of course).
The bug can be witnessed as folllows:
The setmem command should have been commented out for the 16-bit bus case as well, since DDR_PHY_P1_MPODTCTRL should only be used for 64-bit bus case, not 16-bit.
The reason why the setmem command is erroneously uncommented for 16-bit bus width is that cell A176 of the "Realview inc." page has a formula where the condition ("=32") is written to 'prepend the "//" if the bus width is equal to 32' ; since 16 is not equal to 32, the setmem command is erroneously not commented out when the bus width is 16 bit.
If the formula conditon was rewritten to 'prepend "//" if the bus width is different from 64' (<>64), then since 16 is different from 64, the setmem command would correctly be commented out when the bus width is 16 bit.
Hope this clarifies.
Thanks for your kindly explanation!
I will correct the isssue in next release if any.
As this isn't an critical issue and will not block aid using, so I will not update new version in the near future.
No problem! The issue is easy to work around in the .inc by manually commenting out the DDR_PHY_P1_MPODTCTRL line, so fixing the tool fix is indeed not critical.
And anyway, I guess people who use the Script Aid have this page on their bookmarks (or will find it when they hit an issue), so if someone hits a DCD error involving the Script Aid and a 16-bit system DDR, they'll most certainly find this discussion and the solution to their issue.
Once a new version of the Script Aid is out which fixes the issue in the spreadsheet, I will update my posts to add a note in them pointing readers to the fixed version.
Have a nice day!
Will similar sheets compatible with the imx6ul be available?
It is planned and I will update into community like other aid.
The target time is following TO1.1 release time.
Hi, i am using IMX6solo , does this excel sheet support it?
"i.MX6SX DDR3 Script Aid"
if this doesnot, which one i should use?
i.Mx6DQSDL DDR3 Script Aid
if i wanna verify the ddr3 and do the stress test using the "ddr-stress-test-mx6sl.bin", could it work? what is the base address that need to initiate the test?
mx6sl means mx6sololite not mx6solo.
And the stress test tool don't need set base address when you use it.
Please contact local FAE for detailed usage support.
LinWang, I try to access the DDR3 Batch Calibration Guide for i.MX6 on your post, it brings me to the site https://community.freescale.com/docs/DOC-328198 & told me that I am Unauthorized to access & that Access to this place or content is restricted. If you think this is a mistake, please contact your administrator or the person who directed you here.
How can I get access to your batch calibration guide? We have a customer looking for some kind of algorithm or formula for them to apply to get the optimized calibration values over 0 degC, room temperature & 60 degC.
The file had been removed due to need more internal discussion about this topic.
Sorry for inconvenience!
Basicly calibration result should consider different temp and different working mode if any at least.
Thanks Wang Lin for your clarification. I'll let customer know that we do not really have any formula or algorithm, the recommendation is basically to average out the multiple runs over different temperature & different working mode. Let me know if my understanding is incorrect. Thanks.
Yes, your understanding is correct.
No algorithm, only method depend on real application.
I have two i.MX6 boards, with a total of 2GB DDR3 SDRAM (4 x 4GBit), 64-bit bus. I used the DDR Stress Tool V2.51 to calibrate the DDR, running from an SD card, using the following commands in u-boot:
u-boot> dcache off
u-boot> icache off
u-boot> fatload mmc 1:1 0x00907000 ddr-test-uboot-jtag-mx6ul.bin
u-boot> go 0x00907000
For Board #1, the calibration always succeeds. For Board #2, the calibration sometimes fails (~one time of out ten) on:
DDR Calibration failed during Read calibration:
The result is 0x11111111 for the entire run of DDR Calibration failed during Read calibration.
Using the average calibrations from Board #1 and Board #2 (for the successful calibrations), both boards pass the DDR stress test, which was run for 3 hours. Any idea why Board #2 sometimes fails calibration?
I can help aid issue here.
Please rise this board question with a new thread.
Or please contact local FAE for help.
1. The current versions of DDR3 script aid for all IMX6 series processor does not provide separate Drive strength setting for IMX6 and DDR memory which as per my understanding should be provided. Otherwise we need to change it manually when we are using different strength at IMX6 and at Memory. [WL]The aid was generated for quick reference when using different system design. Prefer format as simple as possible for easy hands on. Suggest user fine tune it by themself.
2. Dynamic ODT is default enabled by this script aid but I think it is better to have option to enable or disable dynamic ODT. Nowhere in the script aid it is mentioned that dynamic ODT is enabled. I think this should be clearly indicated.[WL] Same as answer for Q1, this comment is out of scope of this aid. Please understand.
What I have suggested is meant better utilization of script aid. I understand effects on ODT setting on DDR operation and now very well understood IMX6 MMDC Registers it takes hardly one minute for me to change it. But you are saying it is meant for quick reference you should provide details mentioning that what default setting this tool uses. For e.g. a new user or user with relatively less experience might want to set Write timeODT as 40 ohms but he might be under impression that he has set proper ODT of 40 ohms but the fact that Dynamic ODT has been automatically enabled can destroy his purpose without his knowledge.
I'm really surprised to see such comments from you that my comments are out of scope of this aid and NXP is not at all ready to take any inputs which will enhance quality of the tool.
Ladies and Gentlemen -
Would you please publish how to adjust the script for newer DDR parts? For example: I want to select a DDR3L-1866 part and modify the tool to accept. I have the appropriate data, but the script does not accept.
Yes, There is no DDR3-1866 related parameters in aid.
And after internal check and consult DDR vendor, we believe using DDR3-1600 parameters and run on DDR3-1866 grade chip is acceptable.
No potential risk.
That's why I did not update the aid.
During discussion this topic, DDR vendor generally suggest to use DDR3-1066 parameters (which match real working speed).
Hope above info can help you.
Thank You, I will use your recommendations.
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Hello LinWang or Web Manager,
1) The LINK is broken for the "DDR3 Batch Calibration Guide for IMX6". My firefox browser opens another page with "UNAUTHORIZED ACCESS". I do have an account/profile on the NXP community. Is there something I need or is the document unavailable?
2) My custom iMX6QP with DDR3L 4GB PCBA is booting/running BUT I can NOT find NXP documentation/recommendations on "HOW TO finalize DDR3 Calibration Values for PRODUCTION release. My question is: What is BEST Practices in Production for iMX6QP with DDR3L Calibration? Is production test required to CALIBRATE every PCBA, find new values, and then update uboot code/parameters per board (hopefully NO)? Or is there a documented characterization process to establish NORMALIZED Calibration Values for DDR3, that can be FIXED VALUES in the uBoot code for all Production PCBA (hopefully YES)?
Cheers for any help!
Robert Khamashta | Senior Hardware Engineer
ChargePoint | chargepoint.com
+1.669.237.3352 direct | +1.408.202.6336 mobile
Actually the doc had been removed from community.
Would you please contact your local support team from NXP for this request?
I'm trying to calibrate the DDR but i have a problem:
=======DDR configuration==========BOOT_CFG3[5-4]: 0x00, Single DDR channel.DDR type is DDR3Data width: 16, bank num: 8Row size: 16, col size: 10Chip select CSD0 is usedDensity per chip select: 1024MB==================================
What ARM core speed would you like to run?Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz ARM set to 650MHz
Please select the DDR density per chip select (in bytes) on the boardType 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MBFor maximum supported density (4GB), we can only access up to 3.75GB. Type 9 to select this DDR density selected (MB): 1024
Calibration will run at DDR frequency 528MHz. Type 'y' to continue.If you want to run at other DDR frequency. Type 'n'Enter the DDR frequency for calibration [350MHz to 528MHz]:400 The freq you entered was: 400 DDR Freq: 396 MHz
Would you like to run the write leveling calibration? (y/n) Please enter the MR1 value on the initilization script This will be re-programmed into MR1 after write leveling calibration Enter as a 4-digit HEX value, example 0004, then hit enter0004 You have entered: 0x0004Start write leveling calibrationWrite leveling calibration completedMMDC_MPWLDECTRL0 ch0 after write level cal: 0x001A001BMMDC_MPWLDECTRL1 ch0 after write level cal: 0x001F005C
Would you like to run the DQS gating, read/write delay calibration? (y/n)Starting DQS gating calibration...NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. NOT SUPPORTEDNOT SUPPORTEDNOT SUPPORTED. ERROR FOUND, we can't get suitable value !!!!dram test fails for all values.
The DDR stress test can run with an incrementing frequency or at a static freqTo run at a static freq, simply set the start freq and end freq to the same valueWould you like to run the DDR Stress Test (y/n)?
Enter desired START freq (135 to 672 MHz), then hit enter. Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.400 The freq you entered was: 400
Enter desired END freq (135 to 672 MHz), then hit enter.Make sure this is equal to or greater than start freq500 The freq you entered was: 500
Beginning stress test
loop: 1DDR Freq: 396 MHzt0.1: data is addr testAddress of failure: 0x10000000Data was: 0xffffffffBut pattern should match address
Why is the DQS Gatting Calibration "NOT SUPPORTED"?
Actually it was removed, please ask local support for help on this topic.
Can you reproduce the issue on NXP reference board?
If yes, that maybe caused by improper DDR script configuration.
If no, should check case by case.
As it is not script aid itself issue, please ask local NXP support team help.
Is there a version for IMX6UL ?
Thanks for your reply. I solved my issue.
The latest version (0.11) of the script contains following note:
"Do not recommend using 60ohm or lower for any customer design."
Does this means that lower drive strengths (80, 120 or 240ohm) are not recommended or lower impedances (34, 40, 48ohm) are not recommended?
lower driver strength means higher value and lower current.