i.MX6DQ SABRE SDP/B DDR3 Register Programming Aid

Showing results for 
Search instead for 
Did you mean: 

i.MX6DQ SABRE SDP/B DDR3 Register Programming Aid

i.MX6DQ SABRE SDP/B DDR3 Register Programming Aid

This is a detailed programming aid for the registers associated with MMDC initialization. The last sheet formats the register settings for use with ARM RealView ICE. It can also be used with the windows executable for the DDR Stress Test.


Register MMDC_MAARCR is not normally programmed by the initialization script. Freescale recommends leaving it with default values.

This is an advisory to customers who decide to change some of the fields in this register.

A bug has been found with the ARCR_GUARD field. It should always be left programmed to the default 0x0 value. If programmed to a different value, the behavior is unpredictable.

Hello TheAdmiral

Apparently there is an error in the lines 139/140:

setmem /32 0x021b08c0 = 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6

setmem /32 0x021b48c0 = 0x24921492

According to the EB817 the values should be:

0x021B08C0 = 0x24912492

0x021B48C8 = 0x24912492

Could you please double-check these values?



Hi Marco,

Sorry for the confusion.

The setting 0x24912492 is equivalent to the setting 0x24921492.

In setting 0x24912492:

Field CK_FT1_DCC [18:16] = 001

Field CK_FT0_DCC [14:12] = 010

In setting 0x24921492:

Field CK_FT1_DCC [18:16] = 010

Field CK_FT0_DCC [14:12] = 001

Stage FT0 and FT1 are identical stages and they are applied in series.

The setting 010 leaves the duty cycle at 50% duty cycle (default).

The setting 001 leaves the duty cycle at 48.5% low 51.5% high

In both cases, there is only one setting that actually changes duty cycle, so they are both the same.



TheAdmiral​ can i use the above spreadsheet value for i.MX6D because i got some doubt

-> In spreadsheet it is meant for i.MX6Q which is having 4 cores where as i.MX6D has two cores.



Hi Ganesh, gbiradar

Yes this is the spreadsheet to use for the i.MX6Dual processor. It is identical silicon to the i.MX6Quad, except that two cores are disabled. That change does not effect the MMDC complex.

If you are using the i,MX6DualLite processor, then you must use a different programming aid, because the IOMUX register addresses are differerent.



TheAdmiral​ thanks for your reply i'm using dual core which means spreadsheet works fine for me.




Please tell me about two questions.


The recommended setting value is 0.
Why is this?
I thought it was "Differential input mode" setting.

  bit17 DDR_INPUT
   0: CMOS mode (recommended)
   1: Differential input mode"


The recommended setting value is 0.
Why is this?
I thought it was "Differential input mode" setting.



  bit17 DDR_INPUT
   DDR / CMOS Input Mode Field
   Select one out of next values for group: DDRMODE (Pads: DRAM_D[63:0]).
    0: CMOS input type
    1: Differential input mode (recommended)"

Best regards,
Yoshihisa Saito

Version history
Revision #:
1 of 1
Last update:
‎06-24-2015 10:06 PM
Updated by: