The i.MX6 Multi-Mode DDR Controller (MMDC) has profiling capabilities to monitor the operation of the controller. The profiling capability counts certain events related to a specified AXI-ID during a profiling period. The events that can be counted are:
The number of read accesses during the profiling period (MMDCx_MADPSR2[RD_ACC_COUNT] register field)
The number of write accesses during the profiling period (MMDCx_MADPSR3[WR_ACC_COUNT] register field)
The number of bytes read during the profiling period (MMDCx_MADPSR4[RD_BYTES_COUNT] register field)
The number of bytes written during the profiling period (MMDCx_MADPSR5[WR_BYTES_COUNT] register field)
The number of MMDC clock cycles during which the MMDC state machine is busy (MMDCx_MADPSR1[BUSY_COUNT] register field)
BUSY_COUNT is the number of MMDC clock cycles during the profiling period in which the MMDC state machine is not idle. So this is the time the MMDC spends doing any activity, not just read or write data transfers. The MMDC state machine is active whenever there are any read or write requests in the read and write FIFOs. The MMDC is active during many operations that are not reading or writing data such as arbitration of requests, control cycles, bank open/close, etc.
So BUSY_COUNT represents the number of cycles when the controller is busy, not just the number of cycles when the external bus is busy. The number of bytes read and bytes written can be used to determine data throughput and the BUSY_COUNT can be used to determine what part of the time the controller is active/idle. Together these can be used to determine the controller efficiency for a particular application.
For detailed information, see the "MMDC profiling" section of the MMDC chapter in the reference manual for the SoC being used.