i.MX 8/8X/8XLite - LPDDR4 and DDR3L memory compatibility guide

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The purpose of this document is to provide supportive information for selection of suitable LPDDR4 and DDR3L devices that are supported by i.MX 8/8X/8XLite family of processors to aid project feasibility assessment capabilities of customers that are evaluating the SoCs for usage in their products. 

It is strongly recommended to consult with NXP and the respective memory vendor, the final choice of the memory part number to ensure that the device meets all the compatibility, availability, longevity and pricing requirements.

Please note that some of the LPDDR4 devices may not support operation at low speeds and in addition, DQ ODT may not be active, which can impact signal integrity at these speeds. If low speed operation is planned in the use case, please consult with the memory vendor the configuration aspects and possible customization of the memory device so correct functionality is ensured.

In all cases, it is strongly recommended to follow the DRAM layout guidelines outlined in the respective NXP i.MX 8 Hardware Developer's Guide available on NXP.com

The i.MX8/8X/8XL Reference manuals declare that there are 16GB allocated for the DDR. Please note that this is only the address space, which is reserved for the DDR memory in the memory map. This specification does not guarantee that the entire region can be utilized as the maximum achievable densities listed below in the tables are restricted mainly by the addressing capabilities of the DDR controller, width of the data bus and other implementation-specific parameters as well as availability of supported devices on the market.

For any questions related to specific DRAM part numbers please contact the respective DRAM vendor. For any questions regarding the i.MX SoC please contact your support representative or enter a support ticket. 

LPDDR4 - maximum supported densities

Please note that the SoCs only support memory devices that support either the LPDDR4 mode or support both LPDDR4 and LPDDR4X modes. Memory devices that support only the LPDDR4X mode are not supported.

SoC	Package	Max data bus width	Maximum density	Assumed memory organization	Notes
i.MX 8QM/8QP	29x29 mm	32-bit (per controller)	32Gb/4GB (per controller)	dual rank, dual-channel  device with 16-row addresses (R0-R15)	1, 2, 4
i.MX 8QXP/8DXP	21x21 mm	32-bit	32Gb/4GB	dual rank, dual-channel  device with 16-row addresses (R0-R15)	1, 2, 4
i.MX 8QXP/8DXP	17x17 mm	16-bit	16Gb/2GB	dual rank, single-channel  device with 16-row addresses (R0-R15)	1, 2, 3, 4, 9
i.MX 8XLite	15x15 mm	16-bit	32Gb/4GB	dual rank, single channel  device with 17-row addresses (R0-R16)	1, 2, 3, 9

LPDDR4 - list of validated memories

The validation process is an ongoing effort - updates of the table are expected.

SoC	Package	Maximum validated density	Validated part number (vendor)	Notes
i.MX 8QM/8QP	29x29 mm	24Gb/3GB (per controller)	MT53B768M32D4NQ-062 AIT:B (Micron)	-
		32Gb/4GB (per controller)	K4FBE3D4HB-KHCL (Samsung)	10
		32Gb/4GB (per controller)	MT53E1G32D2FW-046 AUT:B (Micron, Z42M)	10
		32Gb/4GB (per controller)	MT53D1024M32D4DT-046 AAT:D (Micron)	-
		16Gb/2GB (per controller)	MT53D512M32D2DS-046 WT:D (Micron)	10
		16Gb/2GB (per controller)	NT6AN512T32AC-J1J (Nanya)	10
		16Gb/2GB (per controller)	NT6AN512T32AC-J1H (Nanya)	10
		32Gb/4GB (per controller)	NT6AN1024F32AC-J2J (Nanya)	10
		32Gb/4GB (per controller)	NT6AN1024F32AC-J2H (Nanya)	10
i.MX 8QXP/8DXP	21x21 mm	24Gb/3GB	MT53B768M32D4NQ-062 AIT:B (Micron)	-
		32Gb/4GB	NT6AN1024F32AC-J2J (Nanya)	10
		32Gb/4GB	NT6AN1024F32AC-J2H (Nanya)	10
		16Gb/2GB	NT6AN512T32AC-J2J (Nanya)	10
		16Gb/2GB	NT6AN512T32AC-J2H (Nanya)	10
		32Gb/4GB	MT53D1024M32D4DT-046 AAT:D (Micron)	-
i.MX 8XLite	15x15 mm	8Gb/1GB	MT53D512M16D1DS 046 AAT ES:D & Z9XGG (Micron)	-
		4Gb/0.5GB	K4F4E164HD-THCL (Samsung)	10
		8Gb/1GB	NT6AN512M16AV-J1I (Nanya)	10

LPDDR4 - list of incompatible devices

Given the limitations mentioned in this document, the following memory devices were identified as incompatible with the particular SoCs as detailed in the following table:

Memory vendor	Part Number	Density	Incompatible SoCs	Incompatibility reason
Samsung	K4FHE3S4HA-KU(H/F)CL	24Gb/3Gb	i.MX8QM/8QP, i.MX8QXP/8DXP	The memory device requires 17th row address bit to function.
Samsung	K4UHE3S4AA-KU(H/F)CL	24Gb/3Gb	i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL	The memory device only supports the LPDDR4X mode.
Samsung	K4UJE3D4AA-KU(H/F)CL	48Gb/6GB	i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL	The memory device only supports the LPDDR4X mode.
Samsung	K4FCE3Q4HB-KU(H/F)CL	64Gb/8GB	i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL	A byte mode memory device.
Samsung	K4UCE3Q4AB-KU(H/F)CL	64Gb/8GB	i.MX8QM/QP, i.MX8QXP/8DXP, i.MX8DXL, i.MX8SXL	A byte mode memory device. The device only supports the LPDDR4X mode.

DDR3L - maximum supported densities

SoC	Package	Max data bus width	Maximum density	Assumed memory organization	Notes
i.MX 8QXP/8DXP	21x21 mm	32-bit	64Gb/8GB	x8, 8Gb device with 16-row addresses and 11 column addresses	5, 6
i.MX 8QXP/8DXP	17x17 mm	16-bit	32Gb/4GB	x8, 8Gb device with 16-row addresses and 11 column addresses	5, 7
i.MX 8XLite	15x15 mm	16-bit	16Gb/2GB	x8, 8Gb device with 16-row addresses and 11 column addresses	5, 8

DDR3L - list of validated memories

The validation process is an ongoing effort -  updates of the table are expected.

SoC	Package	Density	Validated part number (vendor)
i.MX 8QXP/8DXP	21x21 mm	8Gb/1GB	2x MT41K256M16TW-093 IT:P (Micron)
i.MX 8XLite	15x15 mm	4Gb/512MB	MT41K256M16TW-093 IT:P (Micron)

Note 1:

The numbers are based purely on the IP vendor documentation for the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standard JESD209-4A. Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that a DRAM with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.

Note 2:

Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification).

Note 3:

The memory vendors often do not offer so many variants of single-channel memory devices. As an alternative, a dual-channel device with only one channel connected may be used. For example:

A dual-rank, single-channel device with 16-row address bits has a density of 16Gb. If such a device is not available at the chosen supplier, a dual-rank, dual-channel device with 16-row address bits can be used instead. This device has a density of 32 Gb however since only one channel can be connected to the SoC, only half of the density is available (16 Gb).

Usage of more than one discrete memory chip to overcome market constraints is not supported since only point-to-point connections are assumed for LPDDR4.

Note 4:

Devices with 17-row addresses (R0-R16) are not supported by the SoCs. 

Note 5:

The numbers are based purely on the DDR Controller and the DDR PHY, on the settings of the implementation parameters chosen for their integration into the SoC, and on the JEDEC standard JESD79-3E/JESD79-3F. Therefore, they are not backed by validation, unless said otherwise and there is no guarantee that a DRAM with the specific density and/or desired internal organization is offered by the memory vendors. Should the customers choose to use the maximum density and assume it in the intended use case, they do it at their own risk.

Note 6:

The density can be achieved by connecting 8 single rank discrete devices with one 8Gb die each, 4 devices connected to each chip select, or by connecting 4 dual rank discrete devices with two 8Gb dies each. Note that this number of discrete devices significantly exceeds the number of devices used on the validation board (2 discrete devices, not taking into account the device used for ECC) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis hence practically, it is not recommended to use more than 2 discrete DDR3L devices. This corresponds to the maximum density of 16Gb/2GB in the case of the single rank devices containing one 8Gb die or 32Gb/4GB in the case of the dual-rank devices containing two 8Gb dies (x16 8Gb devices with 16-row addresses and 10 column addresses assumed instead of x8 devices in such case).

Note 7:

The density can be achieved by connecting 4 single rank discrete devices with one 8Gb die each, 2 devices connected to each chip select, or by connecting 2 dual rank discrete devices with two 8Gb dies each. Note that the first option exceeds the number of devices used on the validation board (2 discrete devices) therefore, it is not guaranteed that the i.MX would be able to drive the signals with margin to the required voltage levels due to increased loading on the traces. A significant effort would be required in terms of PCB layout and signal integrity analysis, hence practically, it is not recommended to use more than 2 discrete DDR3L devices. This corresponds to the maximum density of 16Gb/2GB in the case of the single rank devices containing one 8Gb die or 32Gb/4GB in the case of the dual-rank devices containing two 8Gb dies.

Note 8:

The density can be achieved by connecting 2 single rank discrete devices with one 8Gb die each to the i.MX. 8XLite supports only one chip select for DDR3L therefore, dual-rank systems are not supported.

Note 9:

For single-channel (x16) memory devices, the current maximum available density in the market is 16Gb/2GB (Q2 2022).

Note 10:

The memory part number did not undergo full JEDEC verification however, it passed all functional testing items.

Additional Links

i.MX 8M Quad/8M Mini/8M Nano/8M Plus - LPDDR4, DDR4 and DDR3L memory compatibility guide