i.MX 6Solo LPDDR2 Registry Settings

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i.MX 6Solo LPDDR2 Registry Settings

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i.MX 6Solo LPDDR2 Registry Settings

Issue: On i.MX 6Solo designs using LPDD2 memory, the correct settings for two important registries may be confusing to determine.

Solution:

1) MMDCx_MDMISC register, LPDDR2_2CH Field: For the i.MX 6Solo processor, this field should always be set to '0'.

Reason: Two channel mode is not possible on this processor. Only channel MMDC0 is connected to external pins.

2) IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET register, DDR_SEL Field: For the i.MX 6Solo processor, this field should always be set to "00".

Reason: A DRAM Warm Reset requires a response from MMDC1, which is not connected externally on the 6Solo processor, so a Warm Reset never complets.

These two issues will be clarified in a subsequent revision of the MCIMX6SDL Reference Manual.

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Comments

Hi,

We are stuck in LPDDR2 single Ch x32 memory interfaced to IMX6 Solo. DDR stress test works well with excel sheet values but uboot fails to work.

Can we have advise on this. Please provide us the values for this.

Yogee

Hi Yogee,

If you are using the DDR Stress test tool and it is working, the parameters you are loading into the processor are already correct.

I think that your real issue is either:

1) The parameters in your u-boot files are not the same parameters that you have determined with the Stress Test tool (they should be the same), or

2) The register parameters are not being loaded in the correct order.

There is a specific order that the parameters must be loaded, and it the order is not followed, then the MMDC will have problems. In general, the order goes:

- IOMUX pin settings.

- MMDC Calibration settings, including ZQ calibration, followed by setting the FRC_MSR bit.

- Loading the main MMDC register settings (and initializing the MMDC by turning it on as the last register loaded in this section)

- Configuring the MR registers of the attached LPDDR2 devices.

If you attach a copy of your u-boot DCD file (the one that contains your initialization parameters), I will review it and point out anything that looks like it could be causing you problems.

Cheers,

Mark

Dear Mark,

Thanks for your comments. Attached are the Flash Header file and script for working LPDDR2 stress test.

Below is working LPDDR2 stress test script.

//=============================================================================  
//init script for i.Mx6S LPDDR2  
//=============================================================================  
// Revision History  
// v01  
//=============================================================================  
  
wait = on  
//=============================================================================  
// Disable    WDOG  
//=============================================================================  

//setmem /16    0x020bc000 =    0x30   

  
//=============================================================================  
// Enable all clocks (they are disabled by ROM code)  
//=============================================================================  

setmem /32    0x020c4068 =    0xffffffff   

setmem /32    0x020c406c =    0xffffffff   

setmem /32    0x020c4070 =    0xffffffff   

setmem /32    0x020c4074 =    0xffffffff   

setmem /32    0x020c4078 =    0xffffffff   

setmem /32    0x020c407c =    0xffffffff   

setmem /32    0x020c4080 =    0xffffffff   

setmem /32    0x020c4084 =    0xffffffff   

  

setmem /32    0x020c4018 =     0x00060324     //DDR clk to 400MHz

  
// Switch PL301_FAST2 to DDR Dual-channel mapping  

//setmem /32     0x00B00000 =     0x1   

  
//=============================================================================  
// IOMUX  
//=============================================================================  
//DDR IO TYPE:  

setmem /32    0x020e0774 =    0x00080000    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE

setmem /32    0x020e0754 =    0x00000000    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE

  
//CLOCK:  

setmem /32    0x020e04ac =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

setmem /32    0x020e04b0 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

  
//ADDRESS:  

setmem /32    0x020e0464 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

setmem /32    0x020e0490 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

setmem /32    0x020e074c =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_ADDDS

  
//Control:  

setmem /32    0x020e0494 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

setmem /32    0x020e04a0 =    0x00000000    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

setmem /32    0x020e04b4 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

setmem /32    0x020e04b8 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

setmem /32    0x020e076c =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_CTLDS

  
//Data Strobes:  

setmem /32    0x020e0750 =    0x00020000    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL

setmem /32    0x020e04bc =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0

setmem /32    0x020e04c0 =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1

setmem /32    0x020e04c4 =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2

setmem /32    0x020e04c8 =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

//setmem /32    0x020e04cc =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4

//setmem /32    0x020e04d0 =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5

//setmem /32    0x020e04d4 =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6

//setmem /32    0x020e04d8 =    0x00003030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7

  
//Data:  

setmem /32    0x020e0760 =    0x00020000    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE

setmem /32    0x020e0764 =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B0DS

setmem /32    0x020e0770 =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B1DS

setmem /32    0x020e0778 =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B2DS

setmem /32    0x020e077c =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B3DS

//setmem /32    0x020e0780 =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B4DS

//setmem /32    0x020e0784 =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B5DS

//setmem /32    0x020e078c =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B6DS

//setmem /32    0x020e0748 =    0x00000030    // IOMUXC_SW_PAD_CTL_GRP_B7DS

  

setmem /32    0x020e0470 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

setmem /32    0x020e0474 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

setmem /32    0x020e0478 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

setmem /32    0x020e047c =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

//setmem /32    0x020e0480 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4

//setmem /32    0x020e0484 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5

//setmem /32    0x020e0488 =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6

//setmem /32    0x020e048c =    0x00000030    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7

  
  
//=============================================================================  
// DDR Controller Registers  
//=============================================================================  
// Manufacturer:    Nanya  
// Device Part Number:    NT6TL128M32AQ-G1  
// Clock Freq.:     400MHz  
// MMDC channels:     MMDC0  
// Density per CS in Gb:     4  
// Chip Selects used:    1  
// Number of Banks:    8  
// Row address:   14  
// Column address:     10  
// Data bus width    32  
//=============================================================================  

setmem /32    0x021b001c =    0x00008000    // MMDC0_MDSCR, set the Configuration request bit during MMDC set up

//setmem /32    0x021b401c =    0x00008000    // MMDC1_MDSCR, set the Configuration request bit during MMDC set up

  

setmem /32    0x021b085c =    0x1B4700C7    //MMDC0_MPZQLP2CTL,LPDDR2 ZQ params

//setmem /32    0x021b485c =    0x1B4700C7    //MMDC1_MPZQLP2CTL,LPDDR2 ZQ params

  
//=============================================================================  
// Calibration setup.  
//=============================================================================  

setmem /32    0x021b0800 =    0xA1390003    // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

  
//ca bus abs delay  

setmem /32    0x021b0890  =    0x00400000    // values of 20,40,50,60,7f tried. no difference seen

//setmem /32    0x021b4890 =    0x00400000    // values of 20,40,50,60,7f tried. no difference seen

  
//Read calibration  

setmem /32    0x021b0848 =    0x40404040    // MPRDDLCTL PHY0

//setmem /32    0x021b4848 =    0x40404040    // MPRDDLCTL PHY1

  
//Write calibration               

setmem /32    0x021b0850 =    0x40404040    // MPWRDLCTL PHY0

//setmem /32    0x021b4850 =    0x40404040    // MPWRDLCTL PHY1

//dqs gating dis  

setmem /32    0x021b083c =    0x20000000   

setmem /32    0x021b0840 =    0x00000000   

//setmem /32    0x021b483c =    0x20000000   

//setmem /32    0x021b4840 =    0x00000000   

  
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)  

setmem /32    0x021b081c =    0x33333333    // DDR_PHY_P0_MPREDQBY0DL3

setmem /32    0x021b0820 =    0x33333333    // DDR_PHY_P0_MPREDQBY1DL3

setmem /32    0x021b0824 =    0x33333333    // DDR_PHY_P0_MPREDQBY2DL3

setmem /32    0x021b0828 =    0x33333333    // DDR_PHY_P0_MPREDQBY3DL3

//setmem /32    0x021b481c =    0x33333333    // DDR_PHY_P1_MPREDQBY0DL3

//setmem /32    0x021b4820 =    0x33333333    // DDR_PHY_P1_MPREDQBY1DL3

//setmem /32    0x021b4824 =    0x33333333    // DDR_PHY_P1_MPREDQBY2DL3

//setmem /32    0x021b4828 =    0x33333333    // DDR_PHY_P1_MPREDQBY3DL3

//write data bit delay: (3 is the reccommended default value, although out of reset value is 0)  

setmem /32    0x021b082c =    0xF3333333    // DDR_PHY_P0_MPREDQBY0DL3

setmem /32    0x021b0830 =    0xF3333333    // DDR_PHY_P0_MPREDQBY1DL3

setmem /32    0x021b0834 =    0xF3333333    // DDR_PHY_P0_MPREDQBY2DL3

setmem /32    0x021b0838 =    0xF3333333    // DDR_PHY_P0_MPREDQBY3DL3

//setmem /32    0x021b482c =    0xF3333333    // DDR_PHY_P1_MPREDQBY0DL3

//setmem /32    0x021b4830 =    0xF3333333    // DDR_PHY_P1_MPREDQBY1DL3

//setmem /32    0x021b4834 =    0xF3333333    // DDR_PHY_P1_MPREDQBY2DL3

//setmem /32    0x021b4838 =    0xF3333333    // DDR_PHY_P1_MPREDQBY3DL3

  
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented  

//setmem /32    0x021b08c0 =    0x24911492    // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6

//setmem /32    0x021b48c0 =    0x24911492   

  
// Complete calibration by forced measurement:            

setmem /32    0x021b08b8 =     0x00000800    // DDR_PHY_P0_MPMUR0, frc_msr

//setmem /32    0x021b48b8 =     0x00000800    // DDR_PHY_P0_MPMUR0, frc_msr

//=============================================================================  
// Calibration setup end  
//=============================================================================  
  
// Channel0 - startng address 0x80000000  

setmem /32    0x021b0004 =    0x00020036    // MMDC0_MDPDC

setmem /32    0x021b0008 =    0x00000000    // MMDC0_MDOTC

setmem /32    0x021b000c =    0x53574133    // MMDC0_MDCFG0

setmem /32    0x021b0010 =    0x00100A82    // MMDC0_MDCFG1

setmem /32    0x021b0014 =    0x00000093    // MMDC0_MDCFG2

  
//MDMISC: RALAT kept to the high level of 5.   
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:   
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3  
//b. Small performence improvment   

setmem /32    0x021b0018 =    0x00001748    // MMDC0_MDMISC

setmem /32    0x021b001c =    0x00008000    //MMDC0_MDSCR, set the Configuration request bit during MMDC set up

setmem /32    0x021b002c =    0x0F9F26D2    // MMDC0_MDRWD

setmem /32    0x021b0030 =    0x00000010    // MMDC0_MDOR

setmem /32    0x021b0038 =    0x00190778    // MMDC0_MDCFG3LP

setmem /32    0x021b0040 =    0x00000017    // Chan0 CS0_END

setmem /32    0x021b0400 =    0x11420000    // MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled

setmem /32    0x021b0000 =    0x83110000    // MMDC0_MDCTL

  
// Channel1 - starting address 0x10000000  

//setmem /32    0x021b4004 =    0x00020036    // MMDC1_MDPDC

//setmem /32    0x021b4008 =    0x00000000    // MMDC1_MDOTC

//setmem /32    0x021b400c =    0x53574133    // MMDC1_MDCFG0

//setmem /32    0x021b4010 =    0x00100A82    // MMDC1_MDCFG1

//setmem /32    0x021b4014 =    0x00000093    // MMDC1_MDCFG2

  
//MDMISC: RALAT kept to the high level of 5.   
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:   
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3  
//b. Small performence improvment   

//setmem /32    0x021b4018 =    0x00001748    // MMDC1_MDMISC

//setmem /32    0x021b401c =    0x00008000    //MMDC1_MDSCR, set the Configuration request bit during MMDC set up

//setmem /32    0x021b402c =    0x0F9F26D2    // MMDC1_MDRWD

//setmem /32    0x021b4030 =    0x00000010    // MMDC1_MDOR

//setmem /32    0x021b4038 =    0x00190778    // MMDC1_MDCFG3LP

//setmem /32    0x021b4040 =    0x00000017    // Chan1 CS0_END

//setmem /32    0x021b4400 =    0x11420000    //MMDC1_MAARCR ADOPT optimized priorities. Dyn jump disabled

//setmem /32    0x021b4000 =    0x83110000    // MMDC1_MDCTL

  
// Channel0 : Configure DDR device:
//CS0  

setmem /32    0x021b001c =    0x003F8030    // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0

setmem /32    0x021b001c =    0xFF0A8030    // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff

setmem /32    0x021b001c =    0x82018030    // MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2

setmem /32    0x021b001c =    0x04028030    // MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4

setmem /32    0x021b001c =    0x02038030    // MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6

//CS1  

//setmem /32    0x021b001c =    0x003F8038    // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0

//setmem /32    0x021b001c =    0xFF0A8038    // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff

//setmem /32    0x021b001c =    0x82018038    // MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2

//setmem /32    0x021b001c =    0x04028038    // MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4

//setmem /32    0x021b001c =    0x02038038    // MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6

  
// Channel1 : Configure DDR device:
//CS0  

//setmem /32    0x021b401c =    0x003F8030    // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0

//setmem /32    0x021b401c =    0xFF0A8030    // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff

//setmem /32    0x021b401c =    0x82018030    // MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2

//setmem /32    0x021b401c =    0x04028030    // MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4

//setmem /32    0x021b401c =    0x02038030    // MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6

//CS1  

//setmem /32    0x021b401c =    0x003F8038    // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0

//setmem /32    0x021b401c =    0xFF0A8038    // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=ff

//setmem /32    0x021b401c =    0x82018038    // MRW: BA=0 CS=1 MR_ADDR=1  MR_OP=c2

//setmem /32    0x021b401c =    0x04028038    // MRW: BA=0 CS=1 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4

//setmem /32    0x021b401c =    0x02038038    // MRW: BA=0 CS=1 MR_ADDR=3  MR_OP=2.drive=240/6

  

setmem /32    0x021b0800 =    0xA1390003    // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

  

setmem /32    0x021b0020 =    0x00001800    // MMDC0_MDREF

//setmem /32    0x021b4020 =    0x00001800    // MMDC1_MDREF

  

setmem /32    0x021b0818 =    0x00000000    // DDR_PHY_P0_MPODTCTRL

//setmem /32    0x021b4818 =    0x00000000    // DDR_PHY_P1_MPODTCTRL

  

setmem /32    0x021b0004 =    0x00025576    // MMDC0_MDPDC now SDCTL power down enabled

//setmem /32    0x021b4004 =    0x00025576    // MMDC0_MDPDC now SDCTL power down enabled

  

setmem /32    0x021b0404 =    0x00011006    // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

//setmem /32    0x021b4404 =    0x00011006    // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

  

setmem /32    0x021b001c =    0x00000000    // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

//setmem /32    0x021b401c =    0x00000000    // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

=============================================================================


  

Below is DCD table in Uboot.

/*

* Copyright (C) 2012 Freescale Semiconductor, Inc.

*

* This program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of

* the License, or (at your option) any later version.

*

* This program is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

* GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*/

#include <config.h>

#include <asm/arch/mx6.h>

#ifdef    CONFIG_FLASH_HEADER

#ifndef CONFIG_FLASH_HEADER_OFFSET

# error "Must define the offset of flash header"

#endif

#define CPU_2_BE_32(l) \

       ((((l) & 0x000000FF) << 24) | \

    (((l) & 0x0000FF00) << 8)  | \

    (((l) & 0x00FF0000) >> 8)  | \

    (((l) & 0xFF000000) >> 24))

#define MXC_DCD_ITEM(i, addr, val)   \

dcd_node_##i:                        \

        .word CPU_2_BE_32(addr) ;     \

        .word CPU_2_BE_32(val)  ;     \

.section ".text.flasheader", "x"

    b    _start

    .org    CONFIG_FLASH_HEADER_OFFSET

ivt_header:       .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */

app_code_jump_v:  .word _start

reserv1:          .word 0x0

dcd_ptr:          .word dcd_hdr

boot_data_ptr:      .word boot_data

self_ptr:         .word ivt_header

#ifdef CONFIG_SECURE_BOOT

app_code_csf:     .word __hab_data

#else

app_code_csf:     .word 0x0

#endif

reserv2:          .word 0x0

boot_data:        .word TEXT_BASE

#ifdef CONFIG_SECURE_BOOT

image_len:        .word __hab_data_end - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET

#else

image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET

#endif

plugin:           .word 0x0

#if defined CONFIG_MX6DL_DDR3

#if defined CONFIG_DDR_32BIT

dcd_hdr:          .word 0x400022D2 /* Tag=0xD2, Len=67*8 + 4 + 4, Ver=0x40 */

write_dcd_cmd:    .word 0x040C21CC /* Tag=0xCC, Len=67*8 + 4, Param=0x04 */

#//=============================================================================           

#// IOMUX           

#//=============================================================================           

#//DDR IO TYPE:           

MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774 ,      0x00080000)    /* OMUXC_SW_PAD_CTL_GRP_DDR_TYPE */

MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754 ,     0x00000000)    /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */

           

#//CLOCK:           

MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0*/

MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1*/

           

#//ADDRESS:           

MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS*/

MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS*/

MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */

           

#//Control:           

MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET*/

MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0 ,     0x00000000)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS*/

MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0*/

MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1*/

MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */

           

#//Data Strobes:           

MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750 ,     0x00020000)    /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL*/

MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc ,     0x00003030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */

MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0 ,     0x00003030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */

MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4 ,     0x00003030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */

MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8 ,     0x00003030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */

           

#//Data:           

MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x760 ,     0x00020000)    /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE*/

MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x764 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_GRP_B0DS */

MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x770 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_GRP_B1DS */

MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x778 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_GRP_B2DS */

MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x77c ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_GRP_B3DS */

MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x470 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0*/

MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x474 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1*/

MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x478 ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2*/

MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x47c ,     0x00000030)    /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3*/

   

#//=============================================================================           

#// DDR Controller Registers           

#//=============================================================================           

#// Manufacturer:    Nanya       

#// Device Part Number:    NT6TL128M32AQ-G1       

#// Clock Freq.:     400MHz       

#// MMDC channels:     MMDC0       

#// Density per CS in Gb:     4       

#// Chip Selects used:    1       

#// Number of Banks:    8       

#// Row address:        14       

#// Column address:     10       

#// Data bus width    32       

#//=============================================================================           

MXC_DCD_ITEM(27, MMDC_P0_BASE_ADDR + 0x01c ,     0x00008000)    /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up    */

MXC_DCD_ITEM(28, MMDC_P0_BASE_ADDR + 0x85c ,     0x1B4700C7)    /* MMDC0_MPZQLP2CTL,LPDDR2 ZQ params*/

#//=============================================================================           

#// Calibration setup.           

#//=============================================================================           

MXC_DCD_ITEM(29, MMDC_P0_BASE_ADDR + 0x800 ,     0xA1390003)    /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.*/

MXC_DCD_ITEM(30, MMDC_P0_BASE_ADDR + 0x890 ,     0x00400000)    /* values of 20,40,50,60,7f tried. no difference seen*/

           

#//Read calibration           

MXC_DCD_ITEM(31, MMDC_P0_BASE_ADDR + 0x848 ,     0x4E4E504C)    /* MPRDDLCTL PHY0*/

           

#//Write calibration                                

MXC_DCD_ITEM(32, MMDC_P0_BASE_ADDR + 0x850 ,     0x3434382E)    /* MPWRDLCTL PHY0*/

#//dqs gating dis           

MXC_DCD_ITEM(33, MMDC_P0_BASE_ADDR + 0x83c ,     0x20000000)   

MXC_DCD_ITEM(34, MMDC_P0_BASE_ADDR + 0x840 ,     0x00000000)   

           

#//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)           

MXC_DCD_ITEM(35, MMDC_P0_BASE_ADDR + 0x81c ,     0x33333333)    /* DDR_PHY_P0_MPREDQBY0DL3*/

MXC_DCD_ITEM(36, MMDC_P0_BASE_ADDR + 0x820 ,     0x33333333)    /* DDR_PHY_P0_MPREDQBY1DL3*/

MXC_DCD_ITEM(37, MMDC_P0_BASE_ADDR + 0x824 ,     0x33333333)    /* DDR_PHY_P0_MPREDQBY2DL3*/

MXC_DCD_ITEM(38, MMDC_P0_BASE_ADDR + 0x828 ,     0x33333333)    /* DDR_PHY_P0_MPREDQBY3DL3*/

#//write data bit delay: (3 is the reccommended default value, although out of reset value is 0)           

MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x82c ,     0xF3333333)    /* DDR_PHY_P0_MPREDQBY0DL3*/

MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x830 ,     0xF3333333)    /* DDR_PHY_P0_MPREDQBY1DL3*/

MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x834 ,     0xF3333333)    /* DDR_PHY_P0_MPREDQBY2DL3*/

MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x838 ,     0xF3333333)    /* DDR_PHY_P0_MPREDQBY3DL3*/

                   

#// Complete calibration by forced measurement:                             

MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x8b8 ,      0x00000800)    /* DDR_PHY_P0_MPMUR0, frc_msr*/

#//=============================================================================           

#// Calibration setup end           

#//=============================================================================           

#// Channel0 - startng address 0x10000000           

MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x004 ,     0x00020036)    /* MMDC0_MDPDC*/

MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x008 ,     0x00000000)    /* MMDC0_MDOTC*/

MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x00c ,     0x53574133)    /* MMDC0_MDCFG0*/

MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x010 ,     0x00100A82)    /* MMDC0_MDCFG1*/

MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x014 ,     0x00000093)    /* MMDC0_MDCFG2*/

           

#//MDMISC: RALAT kept to the high level of 5.            

#//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:            

#//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3           

#//b. Small performence improvment            

MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018 ,     0x00001748)    /* MMDC0_MDMISC*/

MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c ,     0x00008000)    /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up*/

MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x02c ,     0x0F9F26D2)    /* MMDC0_MDRWD*/

MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x030 ,     0x00000010)    /* MMDC0_MDOR*/

MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x038 ,     0x00190778)    /* MMDC0_MDCFG3LP*/

MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x040 ,     0x00000017)    /* Chan0 CS0_END */

MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x400 ,     0x11420000)    /* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled*/

MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x000 ,     0x83110000)    /* MMDC0_MDCTL*/

           

# Channel0 : Configure DDR device:                 

#CS0           

MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x01c ,     0x003F8030)    /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0*/

MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x01c ,     0xFF0A8030)    /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff*/

MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c ,     0x82018030)    /* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=c2*/

MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c ,     0x04028030)    /* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4*/

MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c ,     0x02038030)    /* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6    */

MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x800 ,     0xA1390003)    /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.*/

MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x020 ,     0x00001800)    /* MMDC0_MDREF        */

MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x818 ,     0x00000000)    /* DDR_PHY_P0_MPODTCTRL            */

MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004 ,     0x00025576)    /* MMDC0_MDPDC now SDCTL power down enabled            */

MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x404 ,     0x00011006)    /* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.*/

MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c ,     0x00000000)    /*MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)*/

#endif

#endif

#endif

Yogee

Hi Yogee,

I took a look at both of your files. I see one major difference between the two files:

register 0x021B0848 (Item 31)  Stress test file value is 0x40404040, DCD file value is 0x4E4E504C

register 0x021B0850 (Item 32)  Stress test file value is 0x40404040, DCD file value is 0x3434382E

My question is: How did you come up with these register values for the DCD file? The stress test values are actually the register default values.

Are you using the stress test to determine these values? If the answer is yes, try substituing the values you obtain from the stress test calibration procedure into the stress test file and then running the stress test without performing any calibration tests. If that passes, make sure the DCD register setting have the same value that you are using in the stress test and try again.

The other thing that I didn't see in your DCD file was a line entry to set the CCM clock register 0x020c4018 to a value of 0x00060324. The default value of this register is 0x00064324, and the field being changed is periph_clk2_sel, which I don't think should affect the MMDC, still the field is deliberately being set that way in the stress test file, so it might make a difference.

I don't see anything else wrong with your file at this time. If the register values of the stress test are working and you are not getting any errors, then the same values in the DCD file should be working for you. Hopefully the above will fix your problem.

If not, let me know and I will try to find something else.

Cheers,


Mark

Hi, Yogee :

We encounter the same problem as yours. We are stuck in uboot when using the single channel LPDDR2 (128Mx32). The stress test tool can work fine, but uboot can't success. Do you have any idea and kindly share with us?

Many thanks.

Yao-Hua

Hi Yao-Hua,

I can help you with this issue.

Please attach a copy of the inc file that you are using with the stress test, and a copy of the DCD file you are using with u-boot.

I will look for settings in the DCD file that may be causing problems.

Cheers,

Mark

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‎05-08-2013 12:08 PM
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