Q&A: LVDS inter-channel clock skew

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Q&A: LVDS inter-channel clock skew

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Q&A: LVDS inter-channel clock skew

To connect an FPGA to the i.MX6Q over LVDS.,to connect the 2 LVDS channels in split mode. The datasheet indicates the driver output max skew due to different propagation time of rising and falling edge.

For the sake of the design of their FPGA interface, it would be also interesting to get the skew between the 2 LVDSn_CLK (of the 2 channels) as well as the intrachannel- skew.


Backend database are checked. We can provide the result in the view of design.

Since we do not check inter-channel skew in production, the following may not be guaranteed. 

At the core boundary, we found that, timing skews between every data and clock are within 30ps.

Path from core boundary to PAD are matched by analog layout, should produce some skew well below 30ps also.

As the result, I think, all LVDS signal can be considered as one single group, and skew in datasheet can apply to any signal.

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‎09-23-2013 02:01 AM
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