Q&A: Is there an issue using odd DIV_SELECT values in mx6Q PLL Setting?

cancel
Showing results for 
Search instead for 
Did you mean: 

Q&A: Is there an issue using odd DIV_SELECT values in mx6Q PLL Setting?

No ratings

Q&A: Is there an issue using odd DIV_SELECT values in mx6Q PLL Setting?

Q:Is there an issue using odd DIV_SELECT values?

When setting the CPU clock (maybe others also) in uboot, the code will only use even valuesfor the DIV_SELECT field.

There is nothing in the Reference Manual or Errata that indicates only even values can be used for this field.

There were 2 SR's that had conflicting answers and we are trying to determine what can be used.

The CPU freq setting trying to be achieved is 996MHz.

With a 24MHz source, you need 24MHz x 41.5 = 996MHz.

Since the DIV_SELECT is x2, a value of 83 would be needed.

A:

Below is the DIV_SELECT description of ARM PLL, since the Fin is 24MHz, so there is no odd issue of DVI_SELECT, as 24 / 2 = 12MHz. Such as for 996M, this value is 83, that is fine. "This field controls the pll loop divider. Valid range for divider value: 54-108. Fout = Fin * div_select/2.0."

This document was generated from the following discussion: mx6Q PLL Setting

Labels (1)
Tags (3)
Version history
Revision #:
1 of 1
Last update:
‎09-02-2013 01:06 AM
Updated by: