Some customers often use LVDS LCD with low resolution on i.MX6 platform, such as 320x240, but by defualt , linux bsp doesn't support low frequency pixel clock for LVDS module input.
Question:
When we port LVDS LCD with 320x240 resolution to android4.2.2, we found pixel clock is not correct, it always output 38.9MHz, it is no probem for big resolution , for example 1024x768, but the clock we need for 320x240 LCD is 6.4MHz.
According to the quesiton, Let us check IPU & LDB clock in i.MX6 datasheet at first :
From above table, if ldb clock is from IPU, we will not get 6.4MHz pixel clock, so we will have to adjust its source clock:
The following steps are procedure that ports LVDS LCD with 320x240 resolution to i.MX6Q.
1. Adding LVDS LCD timing structure to ldb.c
static struct fb_videomode ldb_modedb[] = {
{
"LDB-XGA", 60, 320, 240, 155914,
38, 20,
15, 4,
30, 3,
0,
FB_VMODE_NONINTERLACED,
FB_MODE_IS_DETAILED,
},
| { |
"LDB-1080P60", 60, 1920, 1080, 7692,
100, 40,
30, 3,
10, 2,
0,
FB_VMODE_NONINTERLACED,
FB_MODE_IS_DETAILED,},
| }; |
2.Modifying clock source of ldb module
Checking /arch/arm/mach-mx6/clock.c, we can find there are 3 ldb's clock source : &pll5_video_main_clk, &pll2_pfd_352M, &pll2_pfd_400M,
static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
int rev = mx6q_revision();
reg = __raw_readl(MXC_CCM_CS2CDR)
& ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
mux = _get_mux6(parent, &pll5_video_main_clk,
&pll2_pfd_352M, &pll2_pfd_400M,
(rev == IMX_CHIP_REVISION_1_0) ?
&pll3_pfd_540M : /* MX6Q TO1.0 */
&mmdc_ch1_axi_clk[0], /* MX6Q TO1.1 and MX6DL */
&pll3_usb_otg_main_clk, NULL);
reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
__raw_writel(reg, MXC_CCM_CS2CDR);
return 0;
}
By default, pll2_pfd_352M is configured as the clock source of ldb:
clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);
clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M);
We should change the clock source to be pll5_video_main_clk
clk_set_parent(&ldb_di0_clk, &pll5_video_main_clk,);
clk_set_parent(&ldb_di1_clk, &pll5_video_main_clk,);
3. Configuring initial clock in board-mx6q_sabresd.c
static struct ipuv3_fb_platform_data sabresd_fb_data[] = {
{ /*fb0*/
.disp_dev = "ldb",
.interface_pix_fmt = IPU_PIX_FMT_RGB666,
.mode_str = "LDB-XGA",
.default_bpp = 16,
.int_clk = false,
.late_init = false,
}
int_clk=false means LDB clock is from PLL2_PFD_352 or pll5_video_main_clk; int_clk=true mean LDB clock if from IPU.
OK, after doing above steps, LVDS LCD with low resolution should normally work.
Freescale TICS team
Weidong.sun
2015-08-18
