Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

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Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

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Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

This patch made the display no interrupt from uboot to kernel to Android. The IPU and related hardware display interface will only be initialized once in Uboot, the kernel code will skip the IPU initialization.

 

1. Description

    1) Support HDMI, LVDS and LCD output in UBoot.
    2) Support UBoot logo keep from uboot to kernel to Android.
    3) For HDMI, both 720P and 1080P mode were supported.
    4) For LVDS, 1024x768 and 1080P dual channel panels were supported.
    5) The logo file is a 32 bpp bmp file.


2. File List
-- kernel_imx\0001-Keep-uboot-logo-for-Android-boot-supports-HDMI-LCD-a.patch

-- kernel_imx\0002-Bug-fix-for-uboot-logo-keep-patch.patch
   Kernel patch to support the logo keep feature.

-- uboot-imx\0001-Enable-uboot-logo-for-HDMI-LCD-and-LVDS.patch
   Uboot patch to support the logo display.

-- logo.bmp
   Example 32bpp logo file.

-- readme.txt
   this file, please refer to it before use the patches


3. Requirement

- iMX6 SabreSD board.

- Android JB4.2.2_1.1.0-GA UBoot and kernel.


4. How to use

-- Copy the two patch files to Android kernel_imx and uboot-imx folder and apply them.
    $ cd ~/myandroid/kernel_imx/
    $ git apply ./0001-Keep-uboot-logo-for-Android-boot-supports-HDMI-LCD-a.patch
    $ cd ~/myandroid/bootable/bootloader/uboot-imx/
    $ git apply ./0001-Enable-uboot-logo-for-HDMI-LCD-and-LVDS.patch

    $ git apply ./0002-Bug-fix-for-uboot-logo-keep-patch.patch

 

-- Build the new uboot image:
    $ cd ~/myandroid/bootable/bootloader/uboot-imx
    $ export CROSS_COMPILE=~/myandroid/prebuilt/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
    $ export ARCH=arm
    $ make mx6q_sabresd_android_config
    $ make

 

-- Before build new UBoot image, the display type can be selected from file uboot-imx\include\configs\mx6q_sabresd.h
// Select one of the output mode
#define IPU_OUTPUT_MODE_HDMI
//#define IPU_OUTPUT_MODE_LVDS
//#define IPU_OUTPUT_MODE_LCD

 

-- Build the new kernel image:
    $ cd ~/myandroid/kernel_imx
    $ export CROSS_COMPILE=~/myandroid/prebuilt/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
    $ export ARCH=arm
    $ make imx6_android_defconfig
    $ make uImage

 

-- Before "make uImage", make menuconfig can be used to select the display type.
                System Type  --->
                   Freescale MXC Implementations  --->
                      MX6 clk setting for smooth UI transtion from bootloader to kernel  --->
                          Select Display Interface
                             ( )  Smooth UI transtion on LCD, IPU1, DI0
                             ( )  Smooth UI transtion on LVDS, IPU1, DI1
                             (X)  Smooth UI transtion on HDMI, IPU2, DI0

 

-- Uboot parameters for video mode
   1080P HDMI:
      "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24,bpp=32 fb0base=0x27b00000 fbmem=28M hdmi_audio_clk=148500000"

 

   720P HDMI:
      "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24,bpp=32 fb0base=0x27b00000 fbmem=28M hdmi_audio_clk=74250000"

 

   1024x768 LVDS:
      "video=mxcfb0:dev=ldb,LDB-XGA,if=RGB666,bpp=32 fb0base=0x27b00000 fbmem=28M"

 

   800x480 LCD:
      "video=mxcfb0:dev=lcd,CLAA-WVGA,if=RGB565,bpp=32 fb0base=0x27b00000 fbmem=28M"


-- dd the logo.bmp to SD card address 0x100000 and skip the 54 bytes bmp file header.
   sudo dd if=logo.bmp of=/dev/sdc bs=1 seek=1048576 skip=54


5. Note
    1) The logo.bmp file should be 32bpp or 16bpp, and it should be synced with video mode parameters "bpp=xx",

         and uboot config file mx6q_sabresd.h (#define DISPLAY_BPP  xx).

 

    2) The IPU number and DI number are hard coded in kernel file "board-mx6q_sabresd.c".
static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
  .ipu_id = 1,
  .disp_id = 0,
};

static struct fsl_mxc_lcd_platform_data lcdif_data = {
  .ipu_id = 0,
  .disp_id = 0,
  .default_ifmt = IPU_PIX_FMT_RGB565,
};

static struct fsl_mxc_ldb_platform_data ldb_data = {
  .ipu_id = 0,
  .disp_id = 1,
  .ext_ref = 1,
  .mode = LDB_SEP1,
  .sec_ipu_id = 0,
  .sec_disp_id = 0,
};

 

    3) The IPU number and DI number are defined by Macro in Uboot file "include\configs\mx6q_sabresd.h"
#define IPU_NUM   2  // 1 for IPU1, 2 for IPU2.
#define DI_NUM   0  // 0 for DI0, 1 for DI1.

 

    4) The display type used in uboot and kernel must be same, same type, same IPU number, same DI port and
       same resolution.

 

 

[2015-06-29 Update]: JB4.2.2_1.1.0_uboot_logo_keep_patch_2015-06-29.zip

Fix some LVDS issues for iMX6DL.

Also given an example for LVDS0 with DI0.

New Uboot patches:

     0002-Updated-lvds-clock-source-to-pll2_pfd0.-Same-as-kern.patch

     0003-Add-support-for-iMX6DL.patch

 

New kernel patches

     0003-Skip-lvds-re-initialization-for-logo-keep.patch

     0004-Add-examlpe-for-LVDS0-logo-keep.patch

 

 

[2015-08-07 Update]: JB4.2.2_1.1.0_uboot_logo_keep_patch_2015-08-07.zip

Added the new Uboot patch 0004-Correct-the-sequence-to-set-LDB-clock.patch

It can correct the LVDS clock set sequence whch is a known issue that caused no LVDS display sometimes.

 

[2015-09-18 Update]: JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip

Added the patch for Android JB4.3_GA1.1.1 release.

Updated clock usecount, after blank the display, the related clock can be gated off correctly.

Support LVDS clock from PLL5.

 

[2015-12-21 Update]: Added 3.10.53_GA1.1.0 patch: L3.10.53_GA1.1.0_uboot_logo_keep_patch_2015-12-21.zip.

Verified on iMX6DL/Q SabreSD board. It supports LCD and LVDS panels, HDMI patch will be released later.

 

[2016-01-04 Update]: Added 3.10.53_GA1.1.0 patch: L3.10.53_GA1.1.0_uboot_logo_keep_patch_2016-01-04.zip.

Added HDMI display support. Now it supports LCD, LVDS and HDMI displays.

Fixed the video playback issue for boot up.

 

[2016-05-18 Update]: 0001-Fix-the-split-mode-LVDS-panel-no-TX3-signal-issue.patch

An issue was founded, when dual channel 4 lanes LVDS panel was used, in uboot there will be no LVDS TX3 signa on one LVDS port, the attach "0001-Fix-the-split-mode-LVDS-panel-no-TX3-signal-issue.patch" was used to fix this issue, it is based on JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip, for other BSP, please port it manually.

 

[2016-08-29 Update]: 0001-After-reset-IPU-in-SRC-Control-Register-wait-for-res.patch

On some iMX6 chip, after reset the IPU in SRC Control Register, enable IPU at once will cause system hang up, to avoid such issue, software needs wait for IPU reset done by polling the SRC register.

The attach "0001-After-reset-IPU-in-SRC-Control-Register-wait-for-res.patch" was used to fix this issue, it is based on JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip + "0001-Fix-the-split-mode-LVDS-panel-no-TX3-signal-issue.patch", for other BSP, please port it manually.

 

[2017-01-06 Update] Added patch for L4.1.15_GA1.2.0 BSP and Android M6.0.1_GA2.1.0 BSP.

Files: L4.1.15_GA1.2.0_uboot_logo_keep_patch_2017-01-06.zip; M6.0.1_2.1.0_uboot_logo_keep_patch_2017-01-06.zip

Attachments
Comments

Hi,我的平台是i.mx6 双核标准版 的android4.4平台,我打了这些补丁后,uboot的logo可以保持到kernel启动完成,但是在跑android动画前面,会黑屏大概一秒。
   现在我们的产品需要让静态logo保持到开机完成,即android的动画也是换成同一张图片,因此会有在开机过程黑屏一秒左右的现象。

    1.问题初步定位:开机时,init启动surfacefinger 服务时,surfacefinger最终会加载gralloc.imx6.so/gralloc_viv.imx6.so库文件和调用framebuffer_open()函数,

         调用framebuffer_open函数时屏幕黑黑掉,因此从启动surfacefinger到bootanimation第一帧动画开始这段时间lcd会黑屏;

      2.但最终由于发现gralloc_viv.imx6.so我们没有源码无法继续跟踪和测试此问题。

      3.疑问:

         a,基于imx6的android平台是否可以做到开机只显示静态logo,开机到主页过程不闪黑屏?

         b,是否可在第一点我定位的位置去掉刷黑屏动作去解决此问题,如果不能,可否提供其他解决方案?


   uboot 的timing:

/* Select one of the output mode */
    //#define IPU_OUTPUT_MODE_HDMI
    #define IPU_OUTPUT_MODE_LVDS
    //#define IPU_OUTPUT_MODE_LCD
    
    #define LVDS_SPLIT_MODE 1     // For dual channel split mode.
    
    #define CONFIG_FB_BASE  (TEXT_BASE + 0x300000)
    #define UBOOT_LOGO_BMP_ADDR 0x00100000

    //#define CONFIG_IMX_PWM
    //#define IMX_PWM1_BASE     PWM1_BASE_ADDR
    //#define IMX_PWM2_BASE     PWM2_BASE_ADDR

    #define CONFIG_VIDEO_MX5
    #define CONFIG_LCD
    #define CONFIG_CMD_BMP

/* Select LVDS0 bit mapping mode , JEIDA or SPWG */
    #define LVDS_BIT_MAPPING_CH0_JEIDA 1
  //  #define LVDS_BIT_MAPPING_CH0_SPWG 1 /* first pixel */
/* Select LVDS1 bit mapping mode , JEIDA or SPWG */
    //#define LVDS_BIT_MAPPING_CH1_SPWG 1   /* lvds1 not used */
   // #define LVDS_BIT_MAPPING_CH1_SPWG 1   /* second pixel */

    
    #define DISPLAY_WIDTH       960   
    #define DISPLAY_HEIGHT      1280
    #define DISPLAY_BPP         32
    #define DISPLAY_IF_BPP      24  
    #define DISPLAY_HSYNC_START 20
    #define DISPLAY_HSYNC_END   20    
    #define DISPLAY_HSYNC_WIDTH 20
    #define DISPLAY_VSYNC_START 15   
    #define DISPLAY_VSYNC_END   15
    #define DISPLAY_VSYNC_WIDTH 10
    /* pixel clock 30062 */
    #define DISPLAY_PIX_CLOCK  80784000  //(DISPLAY_HSYNC_START + DISPLAY_HSYNC_END + DISPLAY_HSYNC_WIDTH + DISPLAY_WIDTH) * (DISPLAY_VSYNC_START + DISPLAY_VSYNC_END + DISPLAY_VSYNC_WIDTH + DISPLAY_HEIGHT) * refresh rate (60Hz)

    //#define LVDS_SPLIT_MODE  // For dual channel split mode.

    #define DISPLAY_VSYNC_POLARITY          0
    #define DISPLAY_HSYNC_POLARITY          0
    #define DISPLAY_CLOCK_POLARITY          0
    #define DISPLAY_DATA_POLARITY           0
    #define DISPLAY_DATA_ENABLE_POLARITY    1

    #define IPU_NUM            1  // 1 for IPU1, 2 for IPU2.
    #define DI_NUM            0  // 0 for DI0, 1 for DI1.
    #define LVDS_PORT        0  // 0 for LVDS0, 1 for LVDS1. For LVDS display, LVDS_PORT should be same as DI_NUM.
    #define DI_CLOCK_EXTERNAL_MODE  //When clock external mode was defined, the DI clock root will be PLL3 PFD1,
                                //without this macro, the DI root clock is IPU internal clock.
    #define LVDS_CLOCK_SRC_PLL5


kernel:

BOARD_KERNEL_CMDLINE := console=ttymxc0,115200 init=/init video=mxcfb0:dev=ldb,bpp=32  video=mxcfb1:off video=mxcfb2:off fbmem=20M vmalloc=400M  fb0base=0x27b00000 quiet androidboot.console=ttymxc0 androidboot.hardware=freescale

ldb参数:
static struct fsl_mxc_ldb_platform_data ldb_data = {
    .ipu_id = 0,
#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS_LVDS_IPU1_DI0
    .disp_id = 0,
        .ext_ref = 1,
        .mode = LDB_SEP0,
        .sec_ipu_id = 0,
        .sec_disp_id = 1,
#else
        .disp_id = 1,
        .ext_ref = 1,
        .mode = LDB_SEP1,
        .sec_ipu_id = 0,
        .sec_disp_id = 0,
#endif
};

已打补丁:0001-Keep-uboot-logo-for-Android-boot-supports-HDMI-LCD-a.patch
          0001-Enable-uboot-logo-for-HDMI-LCD-and-LVDS.patch

Thanks!

你可以实际测量一下display的信号,看看中间有没有中断过,如果有的话,应该是patch整合的不太对。Patch在开发板上验证过,中间没有黑屏一秒这种问题。

Hi,
我量过i.mx6输出的lvds信号(LVDS_SPLIT_MODE),logo过度的黑屏期间:
tx0,tx1,tx4,tx5无信号;
tx2,tx3,tx6,tx7和clock一直有信号;

从lvds信号看像是输出一个黑屏信号

那应该就是Android层清了一下framebuffer,应该没有1秒那么久的。

Best Regards

发件人: zhangzewei

发送时间: 2018年2月28日 17:04

收件人: Qiang Li - Mpu Se <qiang.li@nxp.com>

主题: Re: - Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

NXP Community <https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.freescale.com%2Fresources%2Fstatics%2F1000%2F35400-NXP-Community-Email-banner-600x75.jpg&data=02%7C01%7Cqiang.li%40nxp.com%7Ccdfb139419d54e0f6f6808d57e8a4790%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636554054730397540&sdata=4xq7V%2FKhXL%2BEO0oAI%2BVdbrtpKYs%2FlrNYBNA4Iy4cgIU%3D&reserved=0>

Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

new comment by zhang zewei<https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.nxp.com%2Fpeople%2Fzhangzewei%3Fet%3Dwatches.email.document_comment&data=02%7C01%7Cqiang.li%40nxp.com%7Ccdfb139419d54e0f6f6808d57e8a4790%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636554054730397540&sdata=uCgQoFlFvjKxGClvTfMq1n3oJ%2FhdzlN7P1cuB6WVOv8%3D&reserved=0> View all comments on this document<https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.nxp.com%2Fdocs%2FDOC-98109%3FcommentID%3D51463%26et%3Dwatches.email.document_comment%23comment-51463&data=02%7C01%7Cqiang.li%40nxp.com%7Ccdfb139419d54e0f6f6808d57e8a4790%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636554054730397540&sdata=NTXe4qVuZEAAmmRyQMlXnMksEuU%2FcU%2F1d5qECmQq6Y4%3D&reserved=0>

不到一秒,860ms左右。
用开发板看了下,从静态logo到android动画出来之间也有一段时间是黑屏的,
但是是14年6月的镜像,如果如你所说,此问题已在开发板上解决,可否提供新的系统镜像验证这个问题?

跟踪过surfaceFinger源码,黑屏动作在framebuffer_open():
      1.SurfaceFlinger::init()->
         mHwc = new HWComposer(this,*static_cast<HWComposer::EventHandler *>(this));->
              HWComposer::loadFbHalModule()->
               framebuffer_open(module, &mFbDev);//此处黑屏

      2.loadFbHalModule()加载的是gralloc.imx6.so,
        framebuffer_open(module, &mFbDev);调用gralloc.imx6.so的gralloc_device_open();
        gralloc_device_open(),加载gralloc_viv.imx6.so

        gralloc_viv.imx6.so 此库我们没有源码,无法跟踪,因此需要FSL帮忙跟踪此问题。

hi,你好,我用的是im6q,Linux。版本是比较新的4.9.11-1.0.0。直接repo下来的。开发板freescale官方开发板。

在uboot里打补丁是失败的。后来手动去掉冲突,但是编译的时候,又报错。

是不是4.9.11-1.0.0不能用这个补丁。那新版我怎么样才能在uboot时候在HDMI的屏幕上显示logo呢?

Hi,

I am running a Dual LVDS Display i.mx6dual system.   Prior to loading these patches, I have verified that I am able to have proper timing and graphics on both displays (1920x720 & 800x480).  I have loaded these patches, but find that only one of the two displays is initialized.   The one display (IPU1 DI0) is initialized, displays the UBOOT Boot Logo, Logo is sustained during Linux boot and then is replaced by the linux app video...

My question is:   Is there a way to have this solution with two displays??   Although I would like to have the graphics of DI1 (IPU2 DI1) blanked at power up in U-Boot, I feel this could be delayed until Linux boot.  The issue is I believe that these patches in the linux kernel were only meant for a single display (LCD, LVDS, or HDMI).  Does anyone have these patches working on a system with two displays??

Thanks in advance!!!

Regards,

Mike Sims

Hi,

   Null pointer appears in gpu test after use "uboot logo keep from uboot to kernel" patch.

   We use "cd /opt/viv_samples/vdk/ && ./tutorial5 -f 100"  to test Gpu function in the imx6q and linux version is 3.0.35.   If we didn't use "uboot logo keep from uboot to kernel" patch ,the gpu test work well; but when use this patch ,a null pointer will appear.

[ 86.290668] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 86.290677] pgd = ba370000
[ 86.290682] [00000000] *pgd=4a23d831, *pte=00000000, *ppte=00000000
[ 86.290697] Internal error: Oops: 817 [#1] PREEMPT SMP
[ 86.290705] Modules linked in:
[ 86.290715] CPU: 1 Not tainted (3.0.35-2508-g54750ff-HNS010700101-03 #15)
[ 86.290736] PC is at wait_for_common+0xec/0x1bc
[ 86.290745] LR is at wait_for_common+0xcc/0x1bc

.....

[ 86.291336] [<8056a104>] (wait_for_common+0xec/0x1bc) from [<80259850>] (mxcfb_pan_display+0x250/0x55c)
[ 86.291367] [<80259850>] (mxcfb_pan_display+0x250/0x55c) from [<80247b80>] (fb_pan_display+0xbc/0x13c)
[ 86.291387] [<80247b80>] (fb_pan_display+0xbc/0x13c) from [<80248534>] (fb_set_var+0x138/0x290)
[ 86.291403] [<80248534>] (fb_set_var+0x138/0x290) from [<80248998>] (do_fb_ioctl+0x30c/0x5d0)
[ 86.291427] [<80248998>] (do_fb_ioctl+0x30c/0x5d0) from [<80100b54>] (do_vfs_ioctl+0x80/0x54c)
[ 86.291446] [<80100b54>] (do_vfs_ioctl+0x80/0x54c) from [<80101058>] (sys_ioctl+0x38/0x5c)
[ 86.291466] [<80101058>] (sys_ioctl+0x38/0x5c) from [<8003ef80>] (ret_fast_syscall+0x0/0x30)

Hi Qiang,

 

We applied  patch for our bsp Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and L...   0001-Fix-the-split-mode-LVDS-panel-no-TX3-signal-issue.patch L4.1.15_GA1.2.0_uboot_logo_keep_patch_2017-01-06.zip

 

Once enable LVDS_SPLIT_MODE in mx6sabre_common.h, LCD seems just display half(see below photo), if Disable LVDS_SPLIT_MODE, it seems display OK.  

 

Linux Kernel use [ fsl,data-mapping = "spwg"], it display correct.

微信图片_20180717112502.jpg

 Dear Frank:

I faced the same issue as you. can you show me which two pins ? thank you very much!

Dear Qiang Li:

   I have some problem when display logo in uboot. Would you give me some advise.

Our designs is based on mx6sabresd board but use IMX6QP,LCD pabel is connect to LVDS0.

I patched M6.0.1_2.1.0-GA UBoot with 0001-Enable-uboot-logo-for-HDMI-LCD-and-LVDS.patch, and port mx6sabre_common.h according the panel(1024*600, RGB888, lvds) which info is attached below.

1.png

2.png

HSD090IFW1- A10 Specification1.0_页面_16.jpg

port code is as below:

#ifdef CONFIG_UBOOT_LOGO_ENABLE
    /* Select one of the output mode */
    /*#define IPU_OUTPUT_MODE_HDMI*/
    #define IPU_OUTPUT_MODE_LVDS
    /*#define IPU_OUTPUT_MODE_LCD*/

...

#ifdef IPU_OUTPUT_MODE_LVDS
    /* For LVDS, 1024*600 resolution */
    #define DISPLAY_WIDTH    1024
    #define DISPLAY_HEIGHT    600
    #define DISPLAY_BPP    32
    #define DISPLAY_IF_BPP    24  /* RGB888 interface */

    #define DISPLAY_HSYNC_START    220
    #define DISPLAY_HSYNC_END    40
    #define DISPLAY_HSYNC_WIDTH    60

    #define DISPLAY_VSYNC_START    20
    #define DISPLAY_VSYNC_END    5
    #define DISPLAY_VSYNC_WIDTH    10

    #define DISPLAY_PIX_CLOCK    51200000  /*(DISPLAY_HSYNC_START + DISPLAY_HSYNC_END + DISPLAY_HSYNC_WIDTH + DISPLAY_WIDTH) * (DISPLAY_VSYNC_START + DISPLAY_VSYNC_END + DISPLAY_VSYNC_WIDTH + DISPLAY_HEIGHT) * refresh rate (60Hz) */

...

    #define DISPLAY_VSYNC_POLARITY            0
    #define DISPLAY_HSYNC_POLARITY            0
    #define DISPLAY_CLOCK_POLARITY            0
    #define DISPLAY_DATA_POLARITY            0
    #define DISPLAY_DATA_ENABLE_POLARITY        1

    #define IPU_NUM            1  /* 1 for IPU1, 2 for IPU2. */
    #define DI_NUM            0  /* 0 for DI0, 1 for DI1. */
    #define LVDS_PORT        0  /* 0 for LVDS0, 1 for LVDS1. */
    #define DI_CLOCK_EXTERNAL_MODE  /* When clock external mode was defined, the DI clock root will be PLL3 PFD1, without this macro, the DI root clock is IPU internal clock. */

But LCD panel display nothing in uboot. which can display correct when android run.

I measured the LVDS signal, LVDS0_TX2,LVDS0_TX3,LVDS0_CLK have wave,but LVDS0_TX0 & LVDS0_TX1 no wave, always a straight line.

@Qiang Canyou give me some advise?

Thanks & BR!

Is this patch available for the Android N7.1.2_2.0.0 BSP?

為什麼我用uboot2017.3月的打上補丁,有很多錯誤,用的是哪個版本的uboot.有源碼嗎

uboot 2017.3需要自行移植patch,无法直接使用的。

我查看了l4.1.15.1.2.0 BSP裡面的uboot,裡面,也沒找到 BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT這個宏的定義。

請問,這個patch是基於uboot2015.4月這個版本嗎? 或者還要加上其他頭文件嗎?

 

Patch is based on the released BSP L4.1.15.1.2.0, the uboot is based on v2015.04 + NXP uboot patches. It is not the default v2015.04 Uboot.

The macro "BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT" is in arch/arm/include/asm/arch-mx6/crm_regs.h.

If you are using the default v2015.04 Uboot without NXP codes, you can't find this file and macro.

thanks,i have found the code.

你好,我按照您的文檔,改了以後,現在我遇到了一個問題,我的LCD,上下左右,的顯示是倒置的,我嘗試改了

 #define DISPLAY_VSYNC_POLARITY 0
 #define DISPLAY_HSYNC_POLARITY 0
#define DISPLAY_CLOCK_POLARITY 1
#define DISPLAY_DATA_POLARITY 0
 #define DISPLAY_DATA_ENABLE_POLARITY 1

這些參數,但是並沒有效果,我想問下,決定屏幕顯示方向的應該修改哪些?

To:

您好,請問,LCD顯示方向,除了跟如下參數有關,還跟什麼有關係?

#define DISPLAY_VSYNC_POLARITY 1

#define DISPLAY_HSYNC_POLARITY 1

#define DISPLAY_CLOCK_POLARITY 0

#define DISPLAY_DATA_POLARITY 0

#define DISPLAY_DATA_ENABLE_POLARITY 0

===================

合肥極友軟件開発有限公司

JiYou Software Development Co., Ltd.张湃

===================

差出人: Qiang_FSL

送信日時: 2019年5月14日 10:06

宛先: pai zhang <zhangpai@jiyou-soft.com>

件名: Re: - Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

<https://community.freescale.com/resources/statics/1000/35400-NXP-Community-Email-banner-600x75.jpg> NXP Community

Patch to support uboot logo keep from uboot to kernel for NXP Linux and Android BSP (HDMI, LCD and LVDS)

new comment by Qiang Li - Mpu Se <https://community.nxp.com/people/Qiang_FSL?et=watches.email.document_comment> View all comments on this document <https://community.nxp.com/docs/DOC-98109?commentID=65323&et=watches.email.document_comment#comment-65323>

Hi pai zhang, 屏的显示方向是屏本身决定的,不是软件设置的。你的问题,应该是屏的方向物理上弄反掉了。

你好,我這uboot logo可以持續顯示到內核了,現在有個問題,不知道怎麼解決

在Starting Xserver,啟動瞬間閃屏一下,是什麼原因導致的?  哪裡配置的不對嗎?? 

Dear Qiang Li - Mpu Se,

We have an issue with this patch on the imx6 solo; it would seem the ipu or ldb is still reset somewhere in Linux.

We tried to fix it but the display is flickers on boot, which is not acceptable to our customer.

I made a post here https://community.nxp.com/message/1159480 

If you could take a look it would be greatly appreciated.

support imx6ul plat?

iMX6UL has no IPU, so the patch can't support it.

hi qiang

   我使用您提供的linux-4.1.15的patch,可以成功的实现logo keep,但是我换成linux-4.9.11的时候,在uboot启动阶段是正常的,进入内核logo就消失了,但是GUI用户程序是可以正常显示的,我修改内核是您的基于linux-4.1.15的patch, 请问,在内核中修改的时候,主要是那几个关键点呢?

主要是相关的clock和IPU DI要避免被重新初始化。

arm-supply和soc-supplay这两个供电节点有影响吗?

clk-imx6q.c的差别比较大。我直接按照4.1的版本修改的,还是进入内核会消失,;

di选择根Uboot一样,ipu部分的代码,我做了比较,4.9和4.1也没有明显的差别.

您尝试过4.9.11的版本吗?

Hi liang yan, no patch for 4.9 and later version kernel, but for debug, you can use "while(1)" dead loop step by step to identify which code modification caused the dsplay disappeared.

HI qiang

   谢谢您的帮助,我在linux-4.9.11的内核上也成功可以保持开机logo了。

Hi Liang, 

 do you mind to share the patch for 4.9? Thanks

Hi Qiang Li,

       We are using a board based on Sabresd but using iMX6QP. Managed to get the uboot screen logo until kernel but just during the kernel initialisation there is a blank for a fraction of second along with slight shift of the logo to the right. I disabled PRE/PRG but even then the issue persists. Can you provide your kind help on this. Thanks

4.9内核中的clk-imx6q.c中注释掉init_ipu_clk(),其他的根Qiang Li提供的patch的修改是一样的。

Hi,

I am not able to download the patches ? Are they not active now ? 

Pls advice where can I download patches? The ones attached to the topic are removed

Hi liang yan,

    Thanks for your help. I just want to clarify the init_ipu_clk function should be commented or not. 

Hello, I want to implement the uboot-2014 partial startup logo, but there is no driver. I found this post by searching and found that you have issued several patches, but they have failed. Can you please send me a copy? thank you very much!

谢谢!

Does the patch work for iMX8M?

No, it is based on IPU hardware which is used on iMX6Solo,6DL,6D,6Q.

hi 强

请教一个关于IPU的问题,我现在这个的色彩空间模式是RGB->RGB, 不使能CSC的功能,在驱动上有修改提高色彩对比的可能性吗?

不能,只有做CSC的时候,才能通过调整系数矩阵的参数来进行处理。

我加了一些log 如下: 我感觉现在就是RGB->RGB, 您帮我看一下,我找了一个imx_csc.c的工具,它是yuv->rgb, 我实验了一下,颜色全部失真了。

我驱动用的lvds RGB24的显示接口, 有啥问题,请帮我指正一下:

Booting Linux on physical CPU 0x0
Linux version 4.9.11-g878147e-dirty (yanl1229@ThinkPad-T470) (gcc version 6.2.0 (GCC) ) #23 SMP PREEMPT Wed Jul 29 13:06:20 CST 2020
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: Freescale i.MX6 DualLite SABRE Smart Device Board
Reserved memory: created CMA memory pool at 0x3c000000, size 320 MiB
OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
Memory policy: Data cache writealloc
On node 0 totalpages: 262144
free_area_init_node: node 0, pgdat 80b69fc0, node_mem_map ab757000
Normal zone: 2048 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 262144 pages, LIFO batch:31
percpu: Embedded 12 pages/cpu @ab720000 s25868 r0 d23284 u49152
pcpu-alloc: s25868 r0 d23284 u49152 alloc=12*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096
Kernel command line: console=ttymxc0,115200 root=/dev/mmcblk3p2 rootwait rw video=mxcfb0:dev=ldb,LDB-WXGA,if=RGB24,bpp=32 ldb=sin0 video=mxcfb1:off
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 699872K/1048576K available (7168K kernel code, 427K rwdata, 1668K rodata, 1024K init, 425K bss, 21024K reserved, 327680K cma-reserved, 0K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
vmalloc : 0xc0800000 - 0xff800000 (1008 MB)
lowmem : 0x80000000 - 0xc0000000 (1024 MB)
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
.text : 0x80008000 - 0x80800000 (8160 kB)
.init : 0x80a00000 - 0x80b00000 (1024 kB)
.data : 0x80b00000 - 0x80b6ad40 ( 428 kB)
.bss : 0x80b6c000 - 0x80bd651c ( 426 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Preemptible hierarchical RCU implementation.
Build-time adjustment of leaf fanout to 32.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
L2C: DT/platform modifies aux control register: 0x32050000 -> 0x32450000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 16 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 16 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76450001
Switching to timer-based delay loop, resolution 333ns
sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 715827882841ns
clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 637086815595 ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=30000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x10100000 - 0x10100058
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (12.00 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
CPU identified as i.MX6DL, silicon rev 1.3
vddarm: bypassed regulator has no supply!
vddarm: failed to get the current voltage(-517)
vddsoc: bypassed regulator has no supply!
vddsoc: failed to get the current voltage(-517)
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
imx6dl-pinctrl 20e0000.iomuxc: initialized IMX pinctrl driver
imx-gpc 20dc000.gpc: pu regulator not ready, retry
mxs-dma 110000.dma-apbh: initialized
SCSI subsystem initialized
libata version 3.00 loaded.
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
2000000.aips-bus:usbphy_nop1 supply vcc not found, using dummy regulator
2000000.aips-bus:usbphy_nop2 supply vcc not found, using dummy regulator
i2c i2c-1: IMX I2C adapter registered
i2c i2c-1: can't use DMA, using PIO instead.
i2c i2c-2: IMX I2C adapter registered
i2c i2c-2: can't use DMA, using PIO instead.
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
imx-ipuv3 2400000.ipu: <ipu_probe>
imx-ipuv3 2400000.ipu: revision is IPUv3H
imx-ipuv3 2400000.ipu: IPU CM Regs = c0811000
imx-ipuv3 2400000.ipu: IPU IC Regs = c081d000
imx-ipuv3 2400000.ipu: IPU IDMAC Regs = c0841000
imx-ipuv3 2400000.ipu: IPU DP Regs = c0849000
imx-ipuv3 2400000.ipu: IPU DC Regs = c0851000
imx-ipuv3 2400000.ipu: IPU DMFC Regs = c0859000
imx-ipuv3 2400000.ipu: IPU DI0 Regs = c0861000
imx-ipuv3 2400000.ipu: IPU DI1 Regs = c0869000
imx-ipuv3 2400000.ipu: IPU SMFC Regs = c0871000
imx-ipuv3 2400000.ipu: IPU CSI0 Regs = c0879000
imx-ipuv3 2400000.ipu: IPU CSI1 Regs = c0881000
imx-ipuv3 2400000.ipu: IPU CPMem = c08a0000
imx-ipuv3 2400000.ipu: IPU TPMem = c08d0000
imx-ipuv3 2400000.ipu: IPU DC Template Mem = c0900000
imx-ipuv3 2400000.ipu: IPU VDI Regs = c0883000
imx-ipuv3 2400000.ipu: ipu_clk = 270000000
ipu_di0 read BS_CLKGEN0 div:16, final_rate:4320000000, prate:270000000
ipu_di1 read BS_CLKGEN0 div:0, final_rate:4320000000, prate:270000000
ipu_task_thread: sched_setaffinity cpu:0.
ipu_task_thread: sched_setaffinity cpu:0.
clocksource: Switched to clocksource mxc_timer1
VFS: Disk quotas dquot_6.6.0
VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
Bus freq driver module loaded
futex hash table entries: 512 (order: 3, 32768 bytes)
workingset: timestamp_bits=30 max_order=18 bucket_order=0
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
fuse init (API version 7.26)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
imx-weim 21b8000.weim: Driver registered.
backlight supply power not found, using dummy regulator
mxc_sdc_fb fb@0: registered mxc display driver ldb
imx-ipuv3 2400000.ipu: Channel already disabled 9
imx-ipuv3 2400000.ipu: Channel already uninitialized 9
imx-ipuv3 2400000.ipu: init channel = 9
imx-ipuv3 2400000.ipu: ipu busfreq high requst.
imx-ipuv3 2400000.ipu: bg_csc_type: 2, fg_csc_type: 0
imx-ipuv3 2400000.ipu: panel size = 1280 x 800
imx-ipuv3 2400000.ipu: pixel clk = 74002000
imx-ipuv3 2400000.ipu: use special clk parent
ipu_di0 read BS_CLKGEN0 div:16, final_rate:1206857136, prate:75428571
ipu_pixel_clk: di_clk_ext:0x0, di_gen reg:0x300000.
ipu_di0 read BS_CLKGEN0 div:16, final_rate:1206857136, prate:75428571
imx-ipuv3 2400000.ipu: round pixel clk:75428571
imx-ipuv3 2400000.ipu: div:1
imx-ipuv3 2400000.ipu: initializing idma ch 23 @ c08a05c0
imx-ipuv3 2400000.ipu: initializing idma ch 23 @ c08a1140 sub cpmem
imx-ipuv3 2400000.ipu: IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)
imx-ipuv3 2400000.ipu: ch 23 word 0 - 00000000 00000000 00000000 E0000000 000C7C9F
imx-ipuv3 2400000.ipu: ch 23 word 1 - 07820000 00F04000 00E3C000 FFF4FFC0 00006208
imx-ipuv3 2400000.ipu: PFS 0x7,
imx-ipuv3 2400000.ipu: BPP 0x0,
imx-ipuv3 2400000.ipu: NPB 0xf
imx-ipuv3 2400000.ipu: FW 1279,
imx-ipuv3 2400000.ipu: FH 799,
imx-ipuv3 2400000.ipu: EBA0 0x3c100000
imx-ipuv3 2400000.ipu: EBA1 0x3c100000
imx-ipuv3 2400000.ipu: Stride 5119
imx-ipuv3 2400000.ipu: scan_order 0
imx-ipuv3 2400000.ipu: uv_stride 8712
imx-ipuv3 2400000.ipu: u_offset 0x0
imx-ipuv3 2400000.ipu: v_offset 0x0
imx-ipuv3 2400000.ipu: Width0 7+1,
imx-ipuv3 2400000.ipu: Width1 7+1,
imx-ipuv3 2400000.ipu: Width2 7+1,
imx-ipuv3 2400000.ipu: Width3 7+1,
imx-ipuv3 2400000.ipu: Offset0 8,
imx-ipuv3 2400000.ipu: Offset1 16,
imx-ipuv3 2400000.ipu: Offset2 24,
imx-ipuv3 2400000.ipu: Offset3 0
imx-ipuv3 2400000.ipu: Channel already disabled 10
imx-ipuv3 2400000.ipu: Channel already uninitialized 10
imx-sdma 20ec000.sdma: no iram assigned, using external mem
imx-sdma 20ec000.sdma: loaded firmware 3.3
pfuze100-regulator 1-0008: Full layer: 2, Metal layer: 1
pfuze100-regulator 1-0008: FAB: 0, FIN: 0
pfuze100-regulator 1-0008: pfuze100 found.
vddpu: supplied by SW1C
usb_otg_vbus: supplied by SWBST
usb_h1_vbus: supplied by SWBST
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 24, base_baud = 5000000) is a IMX
console [ttymxc0] enabled
[drm] Initialized
[drm] Initialized vivante 1.0.0 20120216 on minor 0
brd: module loaded
loop: module loaded
libphy: Fixed MDIO Bus: probed
2188000.ethernet supply phy not found, using dummy regulator
pps pps0: new PPS source ptp0
fec 2188000.ethernet (unnamed net_device) (uninitialized): Invalid MAC address: 00:00:00:00:00:00
fec 2188000.ethernet (unnamed net_device) (uninitialized): Using random MAC address: be:80:00:a2:6b:07
libphy: fec_enet_mii_bus: probed
fec 2188000.ethernet eth0: registered PHC device 0
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-mxc: Freescale On-Chip EHCI Host driver
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usb_ehset_test
2184800.usbmisc supply vbus-wakeup not found, using dummy regulator
ci_hdrc ci_hdrc.1: EHCI Host Controller
ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
file system registered
mousedev: PS/2 mouse device common for all mice
rtc-ds3231 2-0068: Frequency stop was detected
rtc-ds3231 2-0068: IRQ 110 supplied
rtc-ds3231 2-0068: rtc core: registered ds3231 as rtc0
i2c /dev entries driver
IR NEC protocol handler initialized
mxc_v4l2_output v4l2_out: V4L2 device registered as video16
mxc_v4l2_output v4l2_out: V4L2 device registered as video17
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
gspca_main: v2.14.0 registered
imx2-wdt 20c0000.wdog: timeout 60 sec (nowayout=0)
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
sdhci-esdhc-imx 2198000.usdhc: Got CD GPIO
mmc2: SDHCI controller on 2198000.usdhc [2198000.usdhc] using ADMA
mmc3: SDHCI controller on 219c000.usdhc [219c000.usdhc] using ADMA
mxc_vdoa 21e4000.vdoa: iram_base:0xc0820000,iram_paddr:0x905000,size:0x12000
mxc_vdoa 21e4000.vdoa: i.MX Video Data Order Adapter(VDOA) driver probed
caam 2100000.caam: ERA source: CAAMVID.
caam 2100000.caam: AXI pipeline throttling enabled.
caam 2100000.caam: Entropy delay = 3200
caam 2100000.caam: Instantiated RNG4 SH0
mmc3: new DDR MMC card at address 0001
usb 1-1: new high-speed USB device number 2 using ci_hdrc
mmcblk3: mmc3:0001 DG4008 7.28 GiB
mmcblk3boot0: mmc3:0001 DG4008 partition 1 4.00 MiB
mmcblk3boot1: mmc3:0001 DG4008 partition 2 4.00 MiB
caam 2100000.caam: Instantiated RNG4 SH1
caam 2100000.caam: device ID = 0x0a16010000000100 (Era 4)
mmcblk3rpmb: mmc3:0001 DG4008 partition 3 4.00 MiB
mmcblk3: p1 p2
caam 2100000.caam: job rings = 2, qi = 0
caam algorithms registered in /proc/crypto
caam_jr 2101000.jr0: registering rng-caam
snvs-secvio 20cc000.caam-snvs: can't get snvs clock
snvs-secvio 20cc000.caam-snvs: violation handlers armed - non-secure state
hidraw: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
NET: Registered protocol family 26
NET: Registered protocol family 10
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
Key type dns_resolver registered
hub 1-1:1.0: USB hub found
cpu cpu0: regulators not ready, retry
hub 1-1:1.0: 4 ports detected
random: fast init done
imx_epdc_fb 20f4000.epdc: can't get/select pinctrl
vddarm: supplied by SW1AB
vddsoc: supplied by SW1C
imx-gpc 20dc000.gpc: Registered imx-gpc
mxc_vpu 2040000.vpu_fsl: VPU initialized
galcore: clk_get vg clock failed, disable vg!
Galcore version 6.2.2.93313
cpu cpu0: Registered imx6q-cpufreq
imx_thermal 2000000.aips-bus:tempmon: Extended Commercial CPU temperature grade - max:105C critical:100C passive:95C
rtc-ds3231 2-0068: setting system clock to 2020-07-29 04:57:31 UTC (1595998651)
usb_otg_vbus: disabling
hdmi-5v-supply: disabling
CAN XCVR: disabling
SATA_EN: disabling
wifi_pwr_on: disabling
SW4: disabling
EXT4-fs (mmcblk3p2): couldn't mount as ext3 due to feature incompatibilities
EXT4-fs (mmcblk3p2): couldn't mount as ext2 due to feature incompatibilities
EXT4-fs (mmcblk3p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:34.
devtmpfs: mounted
Freeing unused kernel memory: 1024K (80a00000 - 80b00000)
udevd[203]: starting version 3.2
udevd[204]: starting eudev-3.2
EXT4-fs (mmcblk3p2): re-mounted. Opts: data=ordered
Generic PHY 2188000.ethernet:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=2188000.ethernet:01, irq=-1)
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
mxc_v4l2_output v4l2_out: Bypass IC.
mxc_v4l2_output v4l2_out: Bypass IC.
imx-ipuv3 2400000.ipu: Channel already disabled 10
imx-ipuv3 2400000.ipu: Channel already uninitialized 10
imx-ipuv3 2400000.ipu: Channel already disabled 10
imx-ipuv3 2400000.ipu: Channel already uninitialized 10
imx-ipuv3 2400000.ipu: init channel = 10
imx-ipuv3 2400000.ipu: bg_csc_type: 2, fg_csc_type: 2
imx-ipuv3 2400000.ipu: initializing idma ch 27 @ c08a06c0
imx-ipuv3 2400000.ipu: initializing idma ch 27 @ c08a1180 sub cpmem
imx-ipuv3 2400000.ipu: ch 27 word 0 - 00000000 00000000 00000000 E0001800 000C7C9F
imx-ipuv3 2400000.ipu: ch 27 word 1 - 08DA0000 011B4000 00E7C000 F2C27FC0 00082CA0
imx-ipuv3 2400000.ipu: PFS 0x7,
imx-ipuv3 2400000.ipu: BPP 0x3,
imx-ipuv3 2400000.ipu: NPB 0x1f
imx-ipuv3 2400000.ipu: FW 1279,
imx-ipuv3 2400000.ipu: FH 799,
imx-ipuv3 2400000.ipu: EBA0 0x46d00000
imx-ipuv3 2400000.ipu: EBA1 0x46d00000
imx-ipuv3 2400000.ipu: Stride 2559
imx-ipuv3 2400000.ipu: scan_order 0
imx-ipuv3 2400000.ipu: uv_stride 11424
imx-ipuv3 2400000.ipu: u_offset 0x0
imx-ipuv3 2400000.ipu: v_offset 0x0
imx-ipuv3 2400000.ipu: Width0 4+1,
imx-ipuv3 2400000.ipu: Width1 5+1,
imx-ipuv3 2400000.ipu: Width2 4+1,
imx-ipuv3 2400000.ipu: Width3 7+1,
imx-ipuv3 2400000.ipu: Offset0 0,
imx-ipuv3 2400000.ipu: Offset1 5,
imx-ipuv3 2400000.ipu: Offset2 11,
imx-ipuv3 2400000.ipu: Offset3 16
imx-ipuv3 2400000.ipu: DC stop timeout - 1 * 10ms
imx-ipuv3 2400000.ipu: ipu busfreq high release.
ipu_di0 read BS_CLKGEN0 div:16, final_rate:1206857136, prate:75428571
ipu_di0 read BS_CLKGEN0 div:16, final_rate:1206857136, prate:75428571
imx-ipuv3 2400000.ipu: init channel = 9
imx-ipuv3 2400000.ipu: ipu busfreq high requst.
imx-ipuv3 2400000.ipu: bg_csc_type: 2, fg_csc_type: 4
imx-ipuv3 2400000.ipu: panel size = 1280 x 800
imx-ipuv3 2400000.ipu: pixel clk = 74002000
imx-ipuv3 2400000.ipu: use special clk parent
imx-ipuv3 2400000.ipu: round pixel clk:75428571
imx-ipuv3 2400000.ipu: div:1
imx-ipuv3 2400000.ipu: initializing idma ch 23 @ c08a05c0
imx-ipuv3 2400000.ipu: initializing idma ch 23 @ c08a1140 sub cpmem
imx-ipuv3 2400000.ipu: DMFC high resolution has set, will not change
imx-ipuv3 2400000.ipu: ch 23 word 0 - 00000000 00000000 00000000 E0000000 000C7C9F
imx-ipuv3 2400000.ipu: ch 23 word 1 - 08980000 01130000 00E3C000 FFF4FFC0 00006208
imx-ipuv3 2400000.ipu: PFS 0x7,
imx-ipuv3 2400000.ipu: BPP 0x0,
imx-ipuv3 2400000.ipu: NPB 0xf
imx-ipuv3 2400000.ipu: FW 1279,
imx-ipuv3 2400000.ipu: FH 799,
imx-ipuv3 2400000.ipu: EBA0 0x44c00000
imx-ipuv3 2400000.ipu: EBA1 0x44c00000
imx-ipuv3 2400000.ipu: Stride 5119
imx-ipuv3 2400000.ipu: scan_order 0
imx-ipuv3 2400000.ipu: uv_stride 8712
imx-ipuv3 2400000.ipu: u_offset 0x0
imx-ipuv3 2400000.ipu: v_offset 0x0
imx-ipuv3 2400000.ipu: Width0 7+1,
imx-ipuv3 2400000.ipu: Width1 7+1,
imx-ipuv3 2400000.ipu: Width2 7+1,
imx-ipuv3 2400000.ipu: Width3 7+1,
imx-ipuv3 2400000.ipu: Offset0 8,
imx-ipuv3 2400000.ipu: Offset1 16,
imx-ipuv3 2400000.ipu: Offset2 24,
imx-ipuv3 2400000.ipu: Offset3 0
root@imx6dlsabresd:~# random: crng init done

如果你要用yuv->rgb,那么要求你的上层往framebuffer里面画内容的时候,要画成YUV格式,这个要求对UI来讲是不行,一般都是用于Video播放的时候,此时overlay是YUV格式的,解出的YUV420 video数据直接画到overlay里面,然后overlay就可以做yuv->rgb的CSC。

恩,谢谢,上层应用的Qt程序是不能修改格式的,这种情况下,看来想自己增强对比度是不可能了,现在本身就是RGB的,

我想请教一下,驱动中的默认输出的对比度是多少呢,是不是也是有一个控制器在控制。

默认输出就是原始的RGB数据,上层应用画的什么RGB数据,输出就是什么,没有任何数据变换。

谢谢您,明白了

Version history
Revision #:
1 of 1
Last update:
‎11-05-2013 01:31 AM
Updated by: