Patch to Support BT656 and BT1120 Output For i.MX6 BSP

[#1]

Here are two patches to support BT656 and BT1120 output for i.MX6 ipuv3. With this patch, the i.MX6 can support the CVBS output on TV encoder. It is useful for a TV box.

"L3.0.35_1.1.0_GA_bt656_output_patch.zip" is the patch for Freescale L3.0.35_1.1.0_GA_iMX6DQ BSP.

"r13.4.1_bt656_output_patch.zip" is the patch for Freescale Android R13.4.1 BSP.

1. Features supported:

    1) Support BT656(8 bits) and BT1120 (16 bits)interlaced output on display port.
    2) Support both RGB and YUV frame buffer for BT656/BT1120 output.
    3) Support PAL and NTSC mode.
    4) Support on the fly switch between PAL and NTSC mode.
    5) Support CVBS output based on adv7391 TV encoder.

2. Hardware link between iMX6 and adv7391 TV encoder chip.
    IPU1_DI0_DISP_CLK connected to adv7391 CLKIN pin.
    IPU1_DISP0_DAT_23~DISP0_DAT_16 connected to adv7391 P7~P0 pins.
    IPU1_DI0_PIN2 connected to adv7391 HSYNC pin. (option)
    IPU1_DI0_PIN4 connected to adv7391 VSYNC pin. (option)
 
- Android R13.4.1 kernel.

3. How to use

-- Copy the two patch files to kernel folder.
    $ git apply ./0001-Support-BT656-and-BT1120-output-for-iMX6-ipuv3.patch
    $ git apply ./0002-Support-adv739x-TV-encoder-for-BT656-output.patch

-- Select them in kernel config and build the new kernel image:
                    Device Drivers  --->
                      Graphics support  --->
                          [*]   MXC BT656 and BT1120 output
                          [*]   ADV7390/7391 TV Output Encoder

-- Uboot parameters for video mode
   Output BT656 NTSC data to display port with UVYV frame buffer mode:
      "video=mxcfb0:dev=bt656,BT656-NTSC,if=BT656,fbpix=UYVY16"

   Output BT656 NTSC data to display port with RGB565 frame buffer mode:
      "video=mxcfb0:dev=bt656,BT656-NTSC,if=BT656,fbpix=RGB565"

   Output BT656 PAL data to display port with RGB24 frame buffer mode:
      "video=mxcfb0:dev=bt656,BT656-PAL,if=BT656,fbpix=RGB24"

   Output CVBS NTSC signal on adv7391 with UYVY frame buffer mode:
      "video=mxcfb0:dev=adv739x,BT656-NTSC,if=BT656,fbpix=UYVY16"

   Output CVBS PAL signal on adv7391 with RGB565 frame buffer mode:
      "video=mxcfb0:dev=adv739x,BT656-PAL,if=BT656,fbpix=RGB565"

-- Switch between PAL and NTSC
   $ echo D:720x480i-60 > /sys/class/graphics/fb0/mode
   $ echo D:720x576i-50 > /sys/class/graphics/fb0/mode

4. Note
    1) For 8 bits BT656 interface, the default data pins are "DISP0_DAT_23~DISP0_DAT_16", it can also
       be any other continued display data pins, for example if "DISP0_DAT_7~DISP0_DAT_0" are used, the
       macro "BT656_IF_DI_MSB" in "kernel_imx/drivers/mxc/ipu3/ipu_disp.c" should be changed from "23"
       to "7".

    2) For 16 bits BT1120 interface, the default data pins are "DISP0_DAT_23~DISP0_DAT_8", it can also
       be any other continued display data pins, the macro "BT656_IF_DI_MSB" should be modified if the
       hardware pins are changed.

    3) When bt656 interface is the second display for each IPU,1-layer-fb (it can be checked with command
       "$ cat /sys/class/graphics/fbx/fsl_disp_propperty"), the frame buffer can only be YUV format. In this
       case, the IPU DC channel was used for BT656 display, it has no CSC function, so RGB frame buffer was
       not supported.

2013-08-09 updated:

The new release package "L3.0.35_1.1.0_GA_bt656_output_patch_2013-08-09.zip" had fixed the BT656 dual display issue on iMX6S/DL.

Removed the old release package.

2013-09-04 updated:

The new release package "r13.4.1_bt656_output_patch_2013-09-04.zip" had fixed the BT656 dual display issue on iMX6S/DL.

For default, the dual display was tested with HDMI + CVBS, HDMI is the main display and adv739x CVBS output is the second display.

For iMX6DQ which has two IPUs, please assign dual display to two IPUs, for example adv739x is on IPU1 DI0, it is fixed, because hardware pins used for it is fixed. Then we can assign HDMI or LVDS to another IPU (IPU2).

For iMX6S/DL which has only one IPU, since adv739x had used IPU1 DI0, another display should be IPU1 DI1.

2013-09-30 updated:

Added patch for L3.0.35_4.1.0_GA BSP, the file is "L3.0.35_4.1.0_GA_bt656_output_patch_2013-09-30.zip".

2014-07-21 updated:

Added patch for L3.10.17_1.0.0_GA BSP, the file is "L3.10.17_1.0.0_GA_bt656_output_patch_2014-07-21.zip".

2015-01-26 updated:

Updated the IPU microcode for 1080i50 and 1080i60 BT1120 output, the parameters "N" for command BMA is a 8 bits parameters, so its max value is 255, but for 1080i50 and 1080i60 output, it needs more blank data in each line, the "N" will be bigger than 255, the updated IPU microcode can fix this limitation.

The updated file is "IPU_Microcode_Update_for_BT1120_1080i_20150126.zip". You can update the macro "DC_MCODE_BT656_xxx"  and function _ipu_dc_setup_bt656_interlaced() to the old patch if you used BT1120 mode to support 1080i display.

The verified 1080i display mode is:

{

   /* 1080I60 Interlaced output */

  "BT1120-1080I60", 30, 1920, 1080, 13468,

  20, 3,

  20, 2,

  280, 1,

  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

  FB_VMODE_INTERLACED,

  FB_MODE_IS_DETAILED,},

{

  /* 1080I50 Interlaced output */

  "BT1120-1080I50", 25, 1920, 1080, 13468,

  20, 3,

  20, 2,

  720, 1,

  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

  FB_VMODE_INTERLACED,

  FB_MODE_IS_DETAILED,},

2016-01-28 updated:

Updated IPU microcode to align with BT656.4 specification for NTSC output. For other BSP version with NTSC format support, please reference to ipu_disp_update.c for the final microcode.

File "L3.0.35_4.1.0_GA_bt656_output_patch_20160128.zip"., Details, please reference to the readme.txt file in the package.

2016-06-24 update:

Added BT656 and BT1120 progressive mode support.

File "L3.0.35_4.1.0_GA_bt656_output_patch_20160624.zip". Details, please reference to the readme.txt file in the package.

The patch for 3.14.52 GA1.1.0 BSP will be released in next week.

2016-06-27 update:

Add BT656 and BT1120 display patch for 3.14.52 BSP. File "L3.14.52_1.1.0_GA_bt656_output_patch_2016-06-27.zip", details, please reference to the readme.txt in the package.

2017-03-10 update:

Fixed a hard coding DC macro issue for progressive mode. Added patch "0008-Fixed-a-hard-coding-DC-macro-issue-for-progressive-m.patch" in L3.0.35_4.1.0_GA_bt656_output_patch_2017-03-10.zip.

The code in patch "L3.14.52_1.1.0_GA_bt656_output_patch_2016-06-27" is correct.

[tsengshih-chia]

Hi Qiang,

     Could I use this patch for iMX6dl board ?

[qiang_li-mpu_se]

Yes, it can also work on iMX6S and iMX6DL. But there is issue for dual display mode with BT656 ouput support, I planed to give an update in this month to fix it. Currently single BT656/BT1120 output on iMX6S/DL is OK.

[keitanagashima]

Hi Qiang,

I want the patch of dual display mode with BT656 ouput support.

When do you plan to release updated patch?

[qiang_li-mpu_se]

I planned to make dual display with BT656 work on iMX6S/DL before the end of June.

[mariocasto]

Hi Qiang,

I'm using your the patch and the output to adv7391 is good. Now I want to use both HDMI and BT656 to adv7391 and I did the things you told in Update but I can see always BT656 not HDMI.

The uboot paramaters remain the same?

I put also video=mxcfb2:dev=hdmi,1920x1080M@50,if=RGB24 after your uboot params but I can see working only the ADV.

Any suggestion??

Thank you

[qiang_li-mpu_se]

I planned to release the updated code for dual display support on BT656 at the end of July.

[mariocasto]

You mean that this patch still not working? I'm using this on a sabrelite board with iMX6Quad...I forgot to tell you....

[qiang_li-mpu_se]

If you are using iMX6Q which had two IPU, the BT656 is OK for dual display, you can reference to the OTT TVBox reference design, it is OK for HDMI + BT656 on IMX6Q. https://community.freescale.com/docs/DOC-94561

For iMX6S/DL, there is still some issue to enable the dual display with BT656 support, this update will be released at the end of July.

[mariocasto]

I'm not using Freescale Android R13.4.1 BSP but Freescale L3.0.35_1.1.0_GA_iMX6DQ BSP....

[dongchaoxu]

Hi Qiang,

We are working on an automotive project using the iMX.6 DL & iMX.6 Solo SOC with the Android 4.2 BSP.

Is it possible to use ldb as the primary display and bt656 as a second one?

[oliverkuo]

Hi Qiang,

How about the status of dual display with BT656 output on iMX6 Solo for Android build r13.4.1?

I notice you have updated the package of Linux build on 2013-08-09, will you update Android build as well or I have to dig the patch and revise r13.4.1 accordingly by myself?

BTW, we use LCD device as primary display and ADV7391 be second, after I apply r13.4.1 patch, LCD display becomes crushing, is it caused by dual display issue you mentioned on 2013-04-15?

ADV7391 IOMUX setting:

	MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK,
	MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15,
	MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN3,
	MX6DL_PAD_EIM_DA9__IPU1_DISP1_DAT_0,
	MX6DL_PAD_EIM_DA8__IPU1_DISP1_DAT_1,
	MX6DL_PAD_EIM_DA7__IPU1_DISP1_DAT_2,
	MX6DL_PAD_EIM_DA6__IPU1_DISP1_DAT_3,
	MX6DL_PAD_EIM_DA5__IPU1_DISP1_DAT_4,
	MX6DL_PAD_EIM_DA4__IPU1_DISP1_DAT_5,
	MX6DL_PAD_EIM_DA3__IPU1_DISP1_DAT_6,
	MX6DL_PAD_EIM_DA2__IPU1_DISP1_DAT_7,

Thanks,

Oliver

[qiang_li-mpu_se]

The old patch had used pll5 as clock source for both CVBS and other display (such as lcd and hdmi), so when use dual display mode for lcd+cvbs and hdmi+cvbs, then when the second display was enabled, the first display will be impacted, because pll5 frequency will be changed by second display.

We need select different clock source for dual display. The new patch had added such code modification in arch\arm\mach-mx6\clock.c.

LVDS + CVBS output had no such isssue, because lvds clock source is not pll5.

[donfreiling]

Is there a similar patch to support BT1120 for CAPTURE on imx6s?

[qiang_li-mpu_se]

In "https://community.freescale.com/thread/295157", there is some kernel code modification in V4L2 capture driver to support BT1120 capture,
although it is for iMX53 BSP, the same modification can also be applied on iMX6 BSP.

[satoshishimoda]

Hi Qiang,

Do you have a similar patch for MCIMX6Q-SDP with L3.0.35_4.0.0_130424_source BSP to output "progressive" BT656/1120?

Regards,

Satoshi

[qiang_li-mpu_se]

For BT656/BT1120 progressive mode, a new IPU microcode was needed, it is not ready yet.

[oliverkuo]

Hi Qiang,

After apply 3 patches in "r13.4.1_bt656_output_patch_2013-09-04.zip", I still can't make adv7391 work properly on our custom board.

We use LCD as primary display which connect to IPU1 DI0 (DISP0) and ADV7391 connect to IPU1 DI1.

I can't find DISP1's pads definition from user manual; refer to IOMUX tool and iomux-mx6dl.h we connect ADV7391 to the pads as below.

I make ADV7391 as main display to make sure it work properly, boot environment set "video=mxcfb0:dev=adv739x,BT656-NTSC,if=BT656,fbpix=UYVY16"; however no output from ADV7391 and lots of message  "mxc_sdc_fb mxc_sdc_fb.0: timeout when waiting for flip irq" posted on console.

I can't measure clock output on IPU1_DI1_DISP_CLK, only 3.3V output.

ADV7391 setting:

static struct fsl_mxc_lcd_platform_data adv739x_data = {

  .ipu_id = 0,

  .disp_id = 1,

  .default_ifmt = IPU_PIX_FMT_BT656,

};

ADV7391 IOMUX:

	/* ipu1 di1 :: CVBS out */
	MX6DL_PAD_GPIO_18__GPIO_7_13,						/* CVBS_OUT_RST */
	MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK,
	//MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15,
	//MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN3,
	MX6DL_PAD_EIM_DA9__IPU1_DISP1_DAT_0,
	MX6DL_PAD_EIM_DA8__IPU1_DISP1_DAT_1,
	MX6DL_PAD_EIM_DA7__IPU1_DISP1_DAT_2,
	MX6DL_PAD_EIM_DA6__IPU1_DISP1_DAT_3,
	MX6DL_PAD_EIM_DA5__IPU1_DISP1_DAT_4,
	MX6DL_PAD_EIM_DA4__IPU1_DISP1_DAT_5,
	MX6DL_PAD_EIM_DA3__IPU1_DISP1_DAT_6,
	MX6DL_PAD_EIM_DA2__IPU1_DISP1_DAT_7,

Our target is to make LCD as primary display and ADV7391 as secondary output.

Do you have any suggestion?

Thanks for your kindly help.

Oliver

[qiang_li-mpu_se]

Can you check if the adv7391 IPU framebuffer driver is ready with the followed commands:

# cat /sys/class/graphics/fb0/fsl_disp_dev_property

By the way, since you are using BT656 interface on DI1 port, the arch\arm\mach-mx6\clock.c should also be adjusted:

clk_set_parent(&ipu1_di_clk[0], &pll3_pfd_540M);  //for CVBS 27MHz clock

clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);

should be changed to:

clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);

clk_set_parent(&ipu1_di_clk[1], &pll3_pfd_540M);  //for CVBS 27MHz clock

[satoshishimoda]

Dear Qiang Lin,

When will you be able to provide it?

If you need a long time to provide the patch for progressive output, we have to create it by ourselves because our schedule is very tight.

In the case, we need a additional information about the register on the following address, because reference manual (IMX6DQRM Rev.1) doesn't provide the information about it even though the released patch access the address.

Address: 0x02400000+0x00200000+0x00180000

Could you let us know the register information?

Regards,

Satoshi

[qiang_li-mpu_se]

There is no confirmed schedule yet.

Address: 0x02400000 + 0x002000000 + 0x00180000: it is the IPU DC Template Memory, you can reference to reference manual "37.4.7 DC - Display Control"

[oliverkuo]

Hi Qiang,

After change clock setting as you mentioned, I can see output from ADV7391 but the display color is grotesque.

Since ADV7391 uses DISP1_DAT0~7 and these pins are also shared for boot setting, there is a 10k ohm resistor pull to ground.

Would this affects ADV7391 data input accurate? Any suggestion for the hardware connection?

Really thanks for your great support.

Best regards,

Oliver

[qiang_li-mpu_se]

Hi Oliver,
If you had set "fbpix=UYVY16", that means the frame buffer is in YUV format, you should draw it in YUV format. You can try to play video on it, the video playback is OK to support YUV frame buffer.

If you draw the YUV frame buffer with RGB data, there will be color issue.

[oliverkuo]

Hi Qiang,

     Since ADV7391 only support YUV 4:2:2 input, no matter what kind of frame buffer data format, the BT656 interface output should be YUV 4:2:2 with EAV/SAV embedded, I believe BT656 driver is implemented to do so.

     So, if I feel like to output Android desktop to ADV7391, what kind of data format will be filled in frame buffer? RGB,YUV or I cat assign the data format? Do I have to convert the data in frame buffer to fit YUV 4:2:2 output to ADV7391 by myself?

     Furthermore, you said "I can try to paly video on it"! If I set LCD panel as main display, how to play video on ADV7391? I can't find gstream built in Android kernel, may I copy an Ubuntu version into Android kernel or any APK can achieve this?

Thanks for your kindly help.

[gangchen]

Hi  Qiang:

i'm using imx6 dual lite ,android 4.2.2 1.1.0 BSP.and using this patch

this patch fix rear monitor cvbs output to TV_BOX 's SYNC error, and it realy woks.

but during blank opertion, your patch do retry by checking INT_STATE register, till there's no sync error.

this may cost a lot of time , and during this period, front monitor(main lcd display) is ALSO be freezed.

it's terrible. T_T

so, if any suggest or new patch, please notice us, thks.

[qiang_li-mpu_se]

For Android, the frame buffer must be RGB format, so for BY656 output, before sending the frame buffer data to DI port, the IPU DP will be used to convert the RGB frame buffer to YUV422 format.

If you use LCD as main display, the "0003-Enhance-dual-display-support-for-BT656-output.patch" will assign IPU DC for LCD, which has no hardware CSC and assign IPU DP to adv7391 which can support hardware CSC.

From my test, video playback has no issue in Android on the two displays.

[oliverkuo]

Hi Qiang,

I create a thread to discuss my question, could you please leave your advice there, thanks.

https://community.freescale.com/message/360506#360506

[kaisun1]

Dear li:

           I add your patch,and use  uboot parameters : video=mxcfb0:dev=bt656,BT1120-PAL,if=UYVY16,fbpix=RGB565, but the vsync is error.it is not rule.

and other question is how to change this pin:

         IPU1_DI0_PIN2 connected to adv7391 HSYNC pin. (option)

         IPU1_DI0_PIN4 connected to adv7391 VSYNC pin. (option)

Thanks

kai

[qiang_li-mpu_se]

The HSYNC and VSYNC pins are already enabled by the patch, they will output from DI0_PIN2 and DI0_PIN4.

Since BT656 mode doesn't need VSYNC and HSYNC, these signals haven't been checked, just reserved.

The followed DI config code are for them:

    /* COUNTER_2: HSYNC for each line */

    _ipu_di_sync_config(ipu,

      disp,   /* display */

      DI_BT656_SYNC_HSYNC,   /* counter */

      h_total - 1,  /* run count */

      DI_SYNC_CLK, /* run_resolution */

      0,   /* offset */

      DI_SYNC_NONE,  /* offset resolution */

      0,   /* repeat count */

      DI_SYNC_NONE,  /* CNT_CLR_SEL */

      0,   /* CNT_POLARITY_GEN_EN */

      DI_SYNC_NONE,  /* CNT_POLARITY_CLR_SEL */

      DI_SYNC_NONE,  /* CNT_POLARITY_TRIGGER_SEL */

      0,   /* COUNT UP */

      2*div  /* COUNT DOWN */

      );

    /* COUNTER_4: VSYNC for field1 only */

    _ipu_di_sync_config(ipu,

      disp,   /* display */

      DI_BT656_SYNC_VSYNC,   /* counter */

      0,  /* run count */

      DI_BT656_SYNC_HSYNC, /* run_resolution */

      bt656_v_start_width_field0 + height / 2 + bt656_v_end_width_field0,  /*  offset */

      DI_BT656_SYNC_HSYNC,  /* offset resolution */

      1,   /* repeat count */

      DI_BT656_SYNC_IVSYNC,  /* CNT_CLR_SEL */

      0,   /* CNT_POLARITY_GEN_EN */

      DI_SYNC_NONE,  /* CNT_POLARITY_CLR_SEL */

      DI_SYNC_NONE,  /* CNT_POLARITY_TRIGGER_SEL */

      0,   /* COUNT UP */

      2*div  /* COUNT DOWN */

      );

[kaisun1]

Dear li:

             how to achieve 1080i? i add some code on mxc_bt656.c .but my screen not display.

add some code like it:

{

  /* PAL Interlaced output */

  "BT1120-PAL-1080i", 25, 1920,1080, 13468,

  148, 484,

  36, 4,

  88, 5,

  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

  FB_VMODE_INTERLACED,

  FB_MODE_IS_DETAILED,},

does some parameter is error?

Beat Regards

kai

[qiang_li-mpu_se]

Hi sun, that driver can only support BT1120 mode 1080i, and the left_margin, right_margin, up_margin, down_margin in video mode is protocol data, they can't be changed.

You also need make sure your TV encoder chip can support BT1120 input.

[kaisun1]

Hi li :

          Thanks for your reply, that  is a previous questions：i need sabresd board output parallel yuv4:2:2  display, thanks for your help ,720P format  display is OK . but you konw the interlaced is not support,

i communitcte with the TV encoder fae，the chip is support the bt1120 mode,i used your patch ,the 576i format is display ok(but not audio, chip is not support well on bt1120 mode). this TV chip fae let me test 1080i format ,may be have audio，so i added the above code ,but the 1080i is not well,the screen is black. my screen have nothing and then ask for your help. i guess  the parameter is error.

          and i always think the left_margin right_margin etc  through SAV and EAV in display data   is not well. and maybe because of this protocol data  the audio can not  insert the display data( on this chip the audio is insert  on display data gaps).  But anything is to project.

          so can you support the parameter about 1080i， mxc_bt656if.c is only have 576i parameter.

Beat Regard

kai

[qiang_li-mpu_se]

In clock.c, the current clock setting is for 27MHz NTSC and PAL mode, for 1080i, you need the 74.25MHz clock, so you should change the clock source in clock.c.

From

clk_set_parent(&ipu1_di_clk[0], &pll3_pfd_540M);  //for CVBS 27MHz clock

To

clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);

By the way, audio data is not transfered on BT1120 interface, so the audio issue should be the TV chip's issue, non business with BT1120 driver. No matter what, you should not change the margin data in the video mode, those data is for BT656/BT1120 protocol.

[kaisun1]

HI li :

         i  change the clock source on clock.c . and use :setenv bootargs console=ttymxc0,115200 init=/init rw video=mxcfb0:dev=bt656,BT1120-PAL-1080i,if=BT1120,fbpix=RGB565 . but my screen ids no signal.  you have said the margin data:

        {

         /* PAL Interlaced output */

         "BT1120-PAL-1080i", 25, 1920,1080, 13468,

         148, 484,

         36, 4,

         88, 5,

         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

         FB_VMODE_INTERLACED,

         FB_MODE_IS_DETAILED,},

i guess is this parameter is error.  The patch code is no 1080i format, thoes code about 1080i  may be wrong,can your provide a 1080i parameter for me。

Thanks

kai

[qiang_li-mpu_se]

Checked with BT1120-8 protocol, I think you can try the followed parameter for 1080I60 and 1080I50:

{

  /* 1080I60 Interlaced output */

  "BT1120-1080I60", 30, 1920, 1080, 13468,

  20, 3,

  20, 2,

  280, 1,

  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

  FB_VMODE_INTERLACED,

  FB_MODE_IS_DETAILED,},

{

  /* 1080I50 Interlaced output */

  "BT1120-1080I50", 25, 1920, 1080, 13468,

  20, 3,

  20, 2,

  720, 1,

  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

  FB_VMODE_INTERLACED,

  FB_MODE_IS_DETAILED,},

[joshkurland]

I am also interested in BT.1120 1080 capability.  Could you explain how to include this support into the kernel a little further?  I am using Yocto with kernel 3.0.35_4.0.0. 

I have already changed the clock source back to 75MHz, but I do not know where to add the BT1120 parameters.  Should it be placed in drivers/video/mxc/mxc_bt656if.c?  I imagine the boot parameters would look something like mentioned above (video=mxcfb0:dev=bt656,BT1120-PAL-1080i,if=BT1120,fbpix=UYVY16).  Is this correct?  Lastly, is their any support for 1080p? 

Thank you,

Josh Kurland

[qiang_li-mpu_se]

If you just need iMX6 generate BT1120 signal, you can just add the 1080i video mode in file mxc_bt656if.c.

The uboot parameters can be "video=mxcfb0:dev=bt656,BT1120-1080I60,if=BT1120,fbpix=UYVY16" or "video=mxcfb0:dev=bt656,BT1120-1080I60,if=BT1120,fbpix=RGB565". There is no 1080P support for BT1120 mode yet, but you can use VSYNC/HSYNC mode to support 1080P.

[joshkurland]

Thanks for the response.  I copied the 1080i modes to the bottom of struct fb_videomode bt656if_modedb[] in mxc_bt656if.c and modified the u-boot parameters, but I am not getting the correct clock.  Before I load the kernel (still in uboot) the pixel clock is good at 74.25MHz.  After I load the kernel,the pixel clock is stuck at 50MHz.  Also I do not see anything on the HSYNC and VSYNC pins.  Is that supposed to happen or is that a sign something else is wrong?  In arch\arm\mach-mx6\clock.c I have clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);.  Is their anything else I have to set?  I back-ported the patch to run on kernel 3.0.35_4.0.0.  Are you aware of any conflicts that might occur with this?

Thank you,

Josh Kurland

[qiang_li-mpu_se]

I think you should check if the correct mode had been used or not?

$ cat  /sys/class/graphics/fb0/mode

[joshkurland]

With BT1120-1080I60 set using the recommended u-boot parameters, the output of /sys/class/graphics/fb0/mode is D:1920x1080i-30.  I believe this is the correct setting, but the clock is still running at 50MHz.  For BT1120-1080I50 I get D:1920x1080i-25.  I am running this on a SabreLite and a Wandboard quad; I do not have a SabreSD board.  I made the necessary additions to the board-xxx.c and defconfig files.  Can this patch be applied to ALL imx6 boards, or is it specific to the SabreSD?

[qiang_li-mpu_se]

Can you attach your kernel boot log?

[joshkurland]

By kernel boot log do you mean dmesg?  This is a link to dmesg when BT1120-1080I60 is set:  https://drive.google.com/file/d/0B1-NpS0YmbqNZEJJeDFvNFNwTGs/edit?usp=sharing

I am also attaching a file named /var/log/boot:  https://drive.google.com/file/d/0B1-NpS0YmbqNZXJRbW90X054c28/edit?usp=sharing

[qiang_li-mpu_se]

The google drive can't be accessed from China, I had tried your video mode on my SabreSD board, it can get the 74.25MHz pixel clock correctly. Of cource, ipu1_di0 clock should be sourced from PLL5.

[joshkurland]

I am setting clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);  In the line directly above this one I am setting the clock rate as clk_set_rate(&pll5_video_main_clk, 650000000); (line 5458).  Is this the correct value to set PLL5 in order to achieve a 74.25MHz clock?  I have also uploaded my kernel dmesg log to pastebin.com:  imx6 dmesg for BT.1120 - Pastebin.com.  I do not see anything directly defining any video settings.  Could you tell me what I should be looking for?  Lastly, should I move this question to a new thread?  It is starting to become long.  Thank you.

[qiang_li-mpu_se]

Hi Josh, you can set pll5 to 297MHz for 74.25MHz pixel clock.

[joshkurland]

PLL5 clock has been changed, clk_set_rate(&pll5_video_main_clk, 297000000);.  I get the same results.  I also tried to run the clock using PLL3 at 27MHz, just to see what would happen.  This also gave me 50MHz.  Is it possible that something is overriding the clock definitions?  

[timharvey]

Hi Qiang,

I've been using this patch for some time with 3.0.35 and am now updating to the 3.10.17_1.0.0_beta kernel.  Are you planning on creating a patch for that kernel?  Why is this support not part of the Freescale BSP?

Thanks,

Tim

[tongchunyang]

Hi Li

Thanks for your such useful patch to the iMX6 about BT656 functions.

But here I have a problem about the patch into iMX6S customer board with AK8817 encoder chip.

1, Using no external HSYNC/VSYNC, just with BT656 itself . iMX6S can not send correct BT656 signal to AK8817

source like bellow

//-----------------------------------------------------------------------------------

/driver/video/mxc/mxc_bt656if.c

static struct fb_videomode bt656if_modedb[] = {

    {

     /* NTSC Interlaced output */

     "BT656-NTSC", 60, 720, 480, 37037,

     19, 3,

     20, 3,

     276, 1,

     FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

     FB_VMODE_INTERLACED,

     FB_MODE_IS_DETAILED,},

    ......

    ......

};

//------------------------------------------------------------------------------------

/drivers/mxc/ipu3/ipu_disp.c

/* COUNTER_2: HSYNC for each line */

/* COUNTER_2: HSYNC for each line */

_ipu_di_sync_config(ipu,

        disp,         /* display */

        DI_BT656_SYNC_HSYNC,         /* counter */

        h_total - 1,     /* run count */

        DI_SYNC_CLK,    /* run_resolution */

        0,         /* offset */

        DI_SYNC_NONE,     /* offset resolution */

        0,         /* repeat count */

        DI_SYNC_NONE,     /* CNT_CLR_SEL */

        0,         /* CNT_POLARITY_GEN_EN */

        DI_SYNC_NONE,     /* CNT_POLARITY_CLR_SEL */

        DI_SYNC_NONE,     /* CNT_POLARITY_TRIGGER_SEL */

        0,         /* COUNT UP */

        2*div        /* COUNT DOWN */

        );

/* COUNTER_3: internal VSYNC for each frame */

_ipu_di_sync_config(ipu,

        disp,         /* display */

        DI_BT656_SYNC_IVSYNC,         /* counter */

        v_total - 1,     /* run count */

        DI_BT656_SYNC_HSYNC,    /* run_resolution */

        0,             /* offset */

        DI_SYNC_NONE,     /* offset resolution */

        0,         /* repeat count */

        DI_SYNC_NONE,     /* CNT_CLR_SEL */

        0,         /* CNT_POLARITY_GEN_EN */

        DI_SYNC_NONE,     /* CNT_POLARITY_CLR_SEL */

        DI_SYNC_NONE,     /* CNT_POLARITY_TRIGGER_SEL */

        0,         /* COUNT UP */

       0        /* COUNT DOWN */

        );

2, Using external HSYNC/VSYNC, just with BT656 itself . iMX6S can send correct BT656 signal to AK8817

//-----------------------------------------------------------------------------------

/driver/video/mxc/mxc_bt656if.c

static struct fb_videomode bt656if_modedb[] = {

    {

     /* NTSC Interlaced output */

     "BT656-NTSC", 60, 720, 480, 37037,

     19, 3,

     20, 3,

     276, 1,

     0,

     FB_VMODE_INTERLACED,

     FB_MODE_IS_DETAILED,},

    ......

    ......

};

//------------------------------------------------------------------------------------

/drivers/mxc/ipu3/ipu_disp.c

/* COUNTER_2: HSYNC for each line */

/* COUNTER_2: HSYNC for each line */

_ipu_di_sync_config(ipu,

        disp,         /* display */

        DI_BT656_SYNC_HSYNC,         /* counter */

        h_total - 1,     /* run count */

        DI_SYNC_CLK,    /* run_resolution */

        0,         /* offset */

        DI_SYNC_NONE,     /* offset resolution */

        0,         /* repeat count */

        DI_SYNC_NONE,     /* CNT_CLR_SEL */

        0,         /* CNT_POLARITY_GEN_EN */

        DI_SYNC_NONE,     /* CNT_POLARITY_CLR_SEL */

        DI_SYNC_NONE,     /* CNT_POLARITY_TRIGGER_SEL */

        0,         /* COUNT UP */

        20*div        /* COUNT DOWN */

        );

/* COUNTER_3: internal VSYNC for each frame */

_ipu_di_sync_config(ipu,

        disp,         /* display */

        DI_BT656_SYNC_IVSYNC,         /* counter */

        v_total - 1,     /* run count */

        DI_BT656_SYNC_HSYNC,    /* run_resolution */

        0,             /* offset */

        DI_SYNC_NONE,     /* offset resolution */

        0,         /* repeat count */

        DI_SYNC_NONE,     /* CNT_CLR_SEL */

        0,         /* CNT_POLARITY_GEN_EN */

        DI_SYNC_NONE,     /* CNT_POLARITY_CLR_SEL */

        DI_SYNC_NONE,     /* CNT_POLARITY_TRIGGER_SEL */

        0,         /* COUNT UP */

       2*div        /* COUNT DOWN */

        );

Could you please tell me, how to make correct BT656 signals from iMX6 to AK8817 without external HSYNC/VSYNC ?

When use patch on iMX6 Sabre board, there is no such problem.

[qiang_li-mpu_se]

The patch was verified on iMX6S board too, the use case without external HSYNC/VSYNC is the only workable case for this patch, external VSYNC and HSYNC mode hasn't been fine tuned.

I think you should check your hardware for which data pins are used for the BT656 interface, and add the IOMUX setting for these pins.

[tongchunyang]

Hi Li

Sorry for disturbing you again.

As the question just like I took above.

I can see thes two comments

1, /* COUNTER_2: HSYNC for each line */

2, /* COUNTER_3: internal VSYNC for each frame */

My apologies, I am a newer about BT.656 and IPU.

Could you please tell me, HSYNC/VSYNC which set by function ipu_init_sync_panel（）. are internal SYNC or External SYNC?

[qiang_li-mpu_se]

The internal SYNC and external SYNC are just the name, if we don't ouput these signals from IPU DI pins, they are just internal signal, if we enabled output from IPU DI PINs for them, they will be external signal too.