How to locate i.MX6Q pfd issue(ERR006282) without JTAG tools

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How to locate i.MX6Q pfd issue(ERR006282) without JTAG tools

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How to locate i.MX6Q pfd issue(ERR006282) without JTAG tools

When a board is brought up and  the ddr test by link of "https://community.nxp.com/docs/DOC-96412' hashttps://community.nxp.com/docs/DOC-96412' hashttps://community.freescale.com/docs/DOC-96412' hashttps://community.nxp.com/docs/DOC-96412' has been verified, some of boards will have pfd issue(ERR006282). It is suggested that below method could be used to check the issue.The detail steps are:

As boards may have no jtag port, the internal usdhc4 root clock out needs to be remapped. WhenCUP not initialized issue has been seen and in download mode, DDR test tools can be used with the script to remap clock output.

Please check the attached for test script and the empty the binary. Put the two files to DDR stress test tool folder “DDR_Stress_Tester\binary\”. The attached ddr-stress-test-mx6dq.bin is an empty file. Please backup the original file first. After eMMC boot failed and in download mode, run command “DDR_Stress_Tester.exe -t mx6x -df test.inc” on PC side. There is no clock output on GPIO19. For normal test, please erase the eMMC chip and boot the board. It will also fail to boot and run into download mode. After run “DDR_Stress_Tester.exe -t mx6x -df test.inc” , clock can be measured from GPIO19 if no PDF issue happens.

Below is  the details:

The script file.

wait = on

A: Config GPIO19(ENET_ RST_ PHY_B) as CLKO1

setmem /32 0x020E0254 = 0x3    // Config GPIO19(ENET_ RST_ PHY_B) as CLKO1  
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   On your board, it is R112 for the test point.

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B: enabled, CKO1 output drives cko2 clock, divide by 5, usdhc4_clk_root

setmem /32 0x020C4060 = 0x01820101  // CKO2 enabled, CKO1 output drives cko2 clock, divide by 5, usdhc4_clk_root

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And for the normal boot, erase the emmc, and reboot to enter the download mode. There will be no signal output but high voltage on R112. After the script runs, 40Mhz clock will be seen. For the boot fail case, there will be no signal output but high voltage on R112 and 40Mhz clock will be pulled to low.

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1: CKO2 enabled

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2: divide by 5

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3 usdhc4_clk_root

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4: CKO1 output drives cko2 clock

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Comments

Lily and Johnli,

I made modification on English wording and grammar. Please see if the meanings are accuracy.

Thanks,

Yixing

m_c

The attached file test.inc is missing for download.

Could you please help upload again?

Version history
Revision #:
1 of 1
Last update:
‎07-17-2013 12:49 AM
Updated by: