Test environment
i.MX8MP EVK LVDS0
LVDS-HDMI bridge(it6263)
Uboot2022, Uboot2023
Background
Some customers need show logo using LVDS panel.
Current BSP doesn't support LVDS driver in Uboot.
This patch provides i.MX8MPlus LVDS driver support in Uboot.
If you want to connect it to LVDS panel , you need port your lvds panel driver like simple-panel.c
Update
[2022.9.19] Verify on L5.15.32_2.0.0
0001-L5.15.32-Add-i.MX8MP-LVDS-driver-in-uboot
'probe device is failed, ret -2, probe video device failed, ret -19' is caused by below code. It has been merged in attachment.
// /* Only handle devices that have a valid ofnode */
// if (dev_has_ofnode(dev) && !(dev->driver->flags & DM_FLAG_IGNORE_DEFAULT_CLKS)) {
// /*
// * Process 'assigned-{clocks/clock-parents/clock-rates}'
// * properties
// */
// ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE);
// if (ret)
// goto fail;
// }
[2023.3.14] Verify on L5.15.71
0001-L5.15.71-Add-i.MX8MP-LVDS-support-in-uboot
[2023.9.12]
For some panel with low DE, you need uncomment CTRL_INV_DE line and set this bit to 1.
#include <linux/string.h>
@@ -110,9 +111,8 @@ static void lcdifv3_set_mode(struct lcdifv3_priv *priv,
writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_SET));
/* SEC MIPI DSI specific */
- writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
- writel(CTRL_INV_DE, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
-
+ //writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
+ //writel(CTRL_INV_DE, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
}
[2024.5.15]
If you are uing simple-panel.c, need use below patch to set display timing from panel to lcdif controller.
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index f9281d5e83..692c96dcaa 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -18,12 +18,27 @@ struct simple_panel_priv {
struct gpio_desc enable;
};
+/* define your panel timing here and
+ * copy it in simple_panel_get_display_timing */
+static const struct display_timing boe_ev121wxm_n10_1850_timing = {
+ .pixelclock.typ = 71143000,
+ .hactive.typ = 1280,
+ .hfront_porch.typ = 32,
+ .hback_porch.typ = 80,
+ .hsync_len.typ = 48,
+ .vactive.typ = 800,
+ .vfront_porch.typ = 6,
+ .vback_porch.typ = 14,
+ .vsync_len.typ = 3,
+};
+
@@ -100,10 +121,18 @@ static int simple_panel_probe(struct udevice *dev)
return 0;
}
+static int simple_panel_get_display_timing(struct udevice *dev,
+ struct display_timing *timings)
+{
+ memcpy(timings, &boe_ev121wxm_n10_1850_timing, sizeof(*timings));
+
+ return 0;
+}
static const struct panel_ops simple_panel_ops = {
.enable_backlight = simple_panel_enable_backlight,
.set_backlight = simple_panel_set_backlight,
+ .get_display_timing = simple_panel_get_display_timing,
};
static const struct udevice_id simple_panel_ids[] = {
@@ -115,6 +144,7 @@ static const struct udevice_id simple_panel_ids[] = {
{ .compatible = "lg,lb070wv8" },
{ .compatible = "sharp,lq123p1jx31" },
{ .compatible = "boe,nv101wxmn51" },
+ { .compatible = "boe,ev121wxm-n10-1850" },
{ }
};
[2024.7.23]
Update patch for L6.6.23(Uboot2023)
[2025.10.24]
If you are facing 'Enable clock-controller@30380000 failed' error, add clocks in ccm driver.
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 05a7d050be6..38497056344 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -181,6 +181,11 @@ static const char * imx8mp_media_mipi_phy1_ref_sels[] = {"clock-osc-24m", "sys_p
static const char * imx8mp_media_disp_pix_sels[] = {"clock-osc-24m", "video_pll1_out", "audio_pll2_out",
"audio_pll1_out", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
+
+static const char * imx8mp_media_ldb_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll2_100m",
+ "sys_pll1_800m", "sys_pll2_1000m",
+ "clk_ext2", "audio_pll2_out",
+ "video_pll1_out", };
#endif
static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
@@ -321,6 +326,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
#ifndef CONFIG_SPL_BUILD
clk_dm(IMX8MP_CLK_MEDIA_MIPI_PHY1_REF, imx8m_clk_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, base + 0xbd80));
clk_dm(IMX8MP_CLK_MEDIA_DISP1_PIX, imx8m_clk_composite("media_disp1_pix", imx8mp_media_disp_pix_sels, base + 0xbe00));
+ clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX, imx8m_clk_composite("media_disp2_pix", imx8mp_media_disp_pix_sels, base + 0x9300));
+ clk_dm(IMX8MP_CLK_MEDIA_LDB, imx8m_clk_composite("media_ldb", imx8mp_media_ldb_sels, base + 0xbe00));
#endif
clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
@@ -363,7 +370,9 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_MEDIA_APB_ROOT, imx_clk_gate2_shared2("media_apb_root_clk", "media_apb", base + 0x45d0, 0, &share_count_media));
clk_dm(IMX8MP_CLK_MEDIA_AXI_ROOT, imx_clk_gate2_shared2("media_axi_root_clk", "media_axi", base + 0x45d0, 0, &share_count_media));
clk_dm(IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT, imx_clk_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT, imx_clk_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0, &share_count_media));
clk_dm(IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT, imx_clk_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", base + 0x45d0, 0, &share_count_media));
+ clk_dm(IMX8MP_CLK_MEDIA_LDB_ROOT, imx_clk_gate2_shared2("media_ldb_root_clk", "media_ldb", base + 0x45d0, 0, &share_count_media));
#endif
clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
Update LVDS panel demo.
