[6Solox/Freertos]The Patch to fix the LMEM Address for FreeRTOS_BSP_1.0.0_iMX6SX to enable M4 Cache by default

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[6Solox/Freertos]The Patch to fix the LMEM Address for FreeRTOS_BSP_1.0.0_iMX6SX to enable M4 Cache by default

[6Solox/Freertos]The Patch to fix the LMEM Address for FreeRTOS_BSP_1.0.0_iMX6SX to enable M4 Cache by default

The LMEM Base address is 0xE0082000u rather than 0xE0002000u.So please apply the patch to FreeRTOS_BSP_1.0.0_iMX6SX to enable the M4 cache, or the cache was not be enabled by default.It may have the big impact to your product performance.

diff --git a/platform/devices/MCIMX6X/include/MCIMX6X_M4.h
b/platform/devices/MCIMX6X/include/MCIMX6X_M4.h

index 31d6eb2..3b9d240 100644

--- a/platform/devices/MCIMX6X/include/MCIMX6X_M4.h

+++ b/platform/devices/MCIMX6X/include/MCIMX6X_M4.h

@@ -25584,7 +25584,7 @@ typedef struct {

/* LMEM - Peripheral instance base addresses */

/** Peripheral LMEM base address */

-#define LMEM_BASE                                (0xE0002000u)

+#define LMEM_BASE                                (0xE0082000u)

/** Peripheral LMEM base pointer */

#define LMEM                                   ((LMEM_Type *)LMEM_BASE)

#define LMEM_BASE_PTR                            (LMEM)

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FreeRTOS BSP v1.0.1 for 6sx have been released, which have fixed the address issue. The cache was enabled by default for v1.0.1, and not need the patch attached here any more.

http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

Hi Yuan,

Changing the base address to 0xE008_2000. causes my application to hang, presumably on the blocking while in SystemInit (while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK);), is there anything else that requires modification?

Hi Rowan Gifford,

No, we verified the changes on our reference board with the defualt release, and it can work. Can you reproduce the issue on our reference board with our example applications? 

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Last update:
‎06-16-2016 07:59 PM
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