MIPI-DSI Frames check

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MIPI-DSI Frames check

912 Views
Tang_
Contributor II

Hello everyone,

I'm currently trying to enable the MIPI-DSI display based on the Imx8mp Variscite board.

Hoping that someone can help me.

I'm using the following setup : 

  • Driver : panel-rocktech-hx8394f.c updated regarding the TFT (based on a HX8394F controller)
  • DST : imx8mp-var-dart-dt8mcustomboard.dts updated

Using a MIPI analyzer (LA5076 and oscilloscope) I'm able to check that the driver is correctly scheduled and the right behavior during the init phase (during the LP mode) :

Sans-titre

The frame buffer device seems to be ok : 

 

$ cat mode modes name virtual_size
U:720x1280p-0
imx-drmdrmfb
720,1280

 

My device tree blob configuration (MIPI DSI section):

 

/* MIPI-DSI */
&lcdif1 {
        status = "okay";
};

&mipi_dsi {
        status = "okay";
        panel@0 {
                compatible = "rocktech,hx8394f";
                reg = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_hx8394>;
                himax,dsi-lanes = <2>;
                enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 
                reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;   
                vcc-supply = <&reg_hx8394_vcc>;
                iovcc-supply = <&reg_hx8394_iovcc>;
                backlight = <&backlight>;
        };
};
​

 

For information : 

Kernel log : 

 

    0.078695] platform 32e80000.lcd-controller: Fixing up cyclic dependency with 32e60000.mipi_dsi
[    2.135453] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200
[    2.143131] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops)
[    2.394006] WARNING: CPU: 0 PID: 9 at drivers/gpu/drm/bridge/sec-dsim.c:1868 sec_mipi_dsim_irq_handler+0x194/0x214
[    2.394060] pc : sec_mipi_dsim_irq_handler+0x194/0x214
[    2.394219]  sec_mipi_dsim_irq_handler+0x194/0x214
[    2.394318]  mipi_dsi_dcs_exit_sleep_mode+0x0/0x84
[    2.394336]  sec_mipi_dsim_bridge_atomic_enable+0x368/0x520
[    2.394701] imx_sec_dsim_drv 32e60000.mipi_dsi: LP RX timeout
[    2.653625] imx_sec_dsim_drv 32e60000.mipi_dsi: wait pkthdr tx done time out
[    2.653631] imx_sec_dsim_drv 32e60000.mipi_dsi: panel enable failed: -16

 

 

 

 

$ fbset --info

mode "720x1280"
    geometry 720 1280 720 1280 32
    timings 0 0 0 0 0 0 0
    accel true
    rgba 8/16,8/8,8/0,0/0
endmode

Frame buffer device information:
    Name        : imx-drmdrmfb
    Address     : (nil)
    Size        : 3686400
    Type        : PACKED PIXELS
    Visual      : TRUECOLOR
    XPanStep    : 1
    YPanStep    : 1
    YWrapStep   : 0
    LineLength  : 2880
    Accelerator : No

 

 

My question(s) : 

I'm not checking a correctly displayed picture for now, I would like to proceed step by step and I need help to understand why I'm not able and how it would be possible to check the correct behavior in HS mode (after the init sequence)

- Even if the bandwidth of the MIPI analyzer or the oscilloscope is not high enough, why I'm not able to get any samples in HS mode (in order to see something living) ? Would it be due to the input impedance  which collapses the signals ?

- Does someone have solution to measure / check that the frame buffer in correctly "connected" to the MIPI DSI interface ? From software or hardware (instrumental) point of view

I hope I have not forgotten any information. Let me know if you need more details.

I am thankful for any suggestions.

Best regards

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joanxie
NXP TechSupport
NXP TechSupport

you used the third party company board and your own display, it's hard to reproduce this on nxp board, but refer to your logfile, I suggest that you can check your clock settings and timing settings in your dts file, I also attach the application note for your reference

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858 Views
Tang_
Contributor II

I had an issue with an extension board that I made, connecting the board with the TFT using specific connector and allowing to evaluate the previous LCD, with the HX8394 driver.
BTW temporary, we had to switch to an other TFT for testing on table and then all the timing settings and init sequence related to the TFT and the controler.

I move forward in my investigation but I will document this topic when I will receve my adaptation board...

 

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