Driving a 1080x1920 portrait HDMI screen.

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Driving a 1080x1920 portrait HDMI screen.

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cmsd
Contributor III

I need to make a fixed-frequency screen (with a new custom mode line):

{ DRM_MODE("1080x1920", DRM_MODE_TYPE_DRIVER, 137930,
            1080, 1140, 1150, 1185, 0,
            1920, 1928, 1932, 1940, 0,
            DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
            .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },

(in edid_cea_modes[] in imx-hdp.c) work with the iMX8M.

 

My problem is that there is no 137,930 KHz mode in

/* Table 8. HDMI TX clock control settings (pixel clock is output) */
const u32 t28hpc_hdmitx_clock_control_table_pixel_out[T28HPC_HDMITX_CLOCK_CONTROL_TABLE_ROWS_PIXEL_OUT][T28HPC_HDMITX_CLOCK_CONTROL_TABLE_COLS_PIXEL_OUT] = {
{ 27000, 1000, 270000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 80, 0x026, 0x026, 2160000, 0, 2, 2, 2, 4, 135000, 0x3, 27000, 1},
{ 27000, 1250, 337500, 0x03, 0x1, 0x1, 300, 0x0EC, 0x03C, 100, 0x030, 0x030, 2700000, 0, 2, 2, 2, 4, 168750, 0x3, 33750, 1},
{ 27000, 1500, 405000, 0x03, 0x1, 0x1, 360, 0x11C, 0x048, 120, 0x03A, 0x03A, 3240000, 0, 2, 2, 2, 4, 202500, 0x3, 40500, 1},
{ 27000, 2000, 540000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 80, 0x026, 0x026, 2160000, 0, 2, 2, 2, 4, 270000, 0x2, 54000, 1},
{ 54000, 1000, 540000, 0x03, 0x1, 0x1, 480, 0x17C, 0x060, 80, 0x026, 0x026, 4320000, 1, 2, 2, 2, 4, 270000, 0x3, 54000, 1},
{ 54000, 1250, 675000, 0x04, 0x1, 0x1, 400, 0x13C, 0x050, 50, 0x017, 0x017, 2700000, 0, 1, 1, 2, 4, 337500, 0x2, 67500, 1},
{ 54000, 1500, 810000, 0x04, 0x1, 0x1, 480, 0x17C, 0x060, 60, 0x01C, 0x01C, 3240000, 0, 2, 2, 2, 2, 405000, 0x2, 81000, 1},
{ 54000, 2000, 1080000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 40, 0x012, 0x012, 2160000, 0, 2, 2, 2, 1, 540000, 0x1, 108000, 1},
{ 74250, 1000, 742500, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 80, 0x026, 0x026, 5940000, 1, 2, 2, 2, 4, 371250, 0x3, 74250, 1},
{ 74250, 1250, 928125, 0x04, 0x1, 0x1, 550, 0x1B4, 0x06E, 50, 0x017, 0x017, 3712500, 1, 1, 1, 2, 4, 464062, 0x2, 92812, 1},
{ 74250, 1500, 1113750, 0x04, 0x1, 0x1, 660, 0x20C, 0x084, 60, 0x01C, 0x01C, 4455000, 1, 2, 2, 2, 2, 556875, 0x2, 111375, 1},
{ 74250, 2000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 40, 0x012, 0x012, 2970000, 0, 2, 2, 2, 1, 742500, 0x1, 148500, 1},
{ 99000, 1000, 990000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 40, 0x012, 0x012, 3960000, 1, 2, 2, 2, 2, 495000, 0x2, 99000, 1},
{ 99000, 1250, 1237500, 0x03, 0x1, 0x1, 275, 0x0D8, 0x037, 25, 0x00B, 0x00A, 2475000, 0, 1, 1, 2, 2, 618750, 0x1, 123750, 1},
{ 99000, 1500, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 30, 0x00D, 0x00D, 2970000, 0, 2, 2, 2, 1, 742500, 0x1, 148500, 1},
{ 99000, 2000, 1980000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 40, 0x012, 0x012, 3960000, 1, 2, 2, 2, 1, 990000, 0x1, 198000, 1},
{148500, 1000, 1485000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 40, 0x012, 0x012, 5940000, 1, 2, 2, 2, 2, 742500, 0x2, 148500, 1},
{148500, 1250, 1856250, 0x04, 0x1, 0x1, 550, 0x1B4, 0x06E, 25, 0x00B, 0x00A, 3712500, 1, 1, 1, 2, 2, 928125, 0x1, 185625, 1},
{148500, 1500, 2227500, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 30, 0x00D, 0x00D, 4455000, 1, 1, 1, 2, 2, 1113750, 0x1, 222750, 1},
{148500, 2000, 2970000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 40, 0x012, 0x012, 5940000, 1, 2, 2, 2, 1, 1485000, 0x1, 297000, 1},
{198000, 1000, 1980000, 0x03, 0x1, 0x1, 220, 0x0AC, 0x02C, 10, 0x003, 0x003, 1980000, 0, 1, 1, 2, 1, 990000, 0x0, 198000, 1},
{198000, 1250, 2475000, 0x03, 0x1, 0x1, 550, 0x1B4, 0x06E, 25, 0x00B, 0x00A, 4950000, 1, 1, 1, 2, 2, 1237500, 0x1, 247500, 1},
{198000, 1500, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 15, 0x006, 0x005, 2970000, 0, 1, 1, 2, 1, 1485000, 0x0, 297000, 1},
{198000, 2000, 3960000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 20, 0x008, 0x008, 3960000, 1, 1, 1, 2, 1, 1980000, 0x0, 396000, 1},
{297000, 1000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 10, 0x003, 0x003, 2970000, 0, 1, 1, 2, 1, 1485000, 0x0, 297000, 1},
{297000, 1500, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 15, 0x006, 0x005, 4455000, 1, 1, 1, 2, 1, 2227500, 0x0, 445500, 1},
{297000, 2000, 5940000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 20, 0x008, 0x008, 5940000, 1, 1, 1, 2, 1, 2970000, 0x0, 594000, 1},
{594000, 1000, 5940000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 10, 0x003, 0x003, 5940000, 1, 1, 1, 2, 1, 2970000, 0x0, 594000, 1},
{594000, 750, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 10, 0x003, 0x003, 4455000, 1, 1, 1, 2, 1, 2227500, 0x0, 445500, 0},
{594000, 625, 3712500, 0x04, 0x1, 0x1, 550, 0x1B4, 0x06E, 10, 0x003, 0x003, 3712500, 1, 1, 1, 2, 1, 1856250, 0x0, 371250, 0},
{594000, 500, 2970000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 10, 0x003, 0x003, 5940000, 1, 1, 1, 2, 2, 1485000, 0x1, 297000, 1},

in t28hpc_hdmitx_table.c.

 

I need to learn:

1. Is the table the full extent of what the GPU/DCSS can do?  (In which case it can't drive my 1080x1920 portrait screen.)

2. If 137,930 KHz modes are physically possible in the DCSS, where do I get the other numbers from?  (I assume that they're register settings.)

 

Update:

By spotting patterns, I've made a plausible row for t28hpc_hdmitx_clock_control_table_pixel_out[]:

{138375, 1000, 1383750, 0x03, 0x1, 0x1, 615, 0x1E8, 0x07B, 40, 0x012, 0x012, 5535000, 1, 2, 2, 2, 2, 691875, 0x2, 138375, 1},

which is only 0.3% too fast.  (The second-nearest integer solution is 0.5% too slow.)

 

The next issue is how to generate a 138,375 KHz row for t28hpc_hdmitx_pll_tuning_table_pixel_out[][] in t28hpc_hdmitx_table.c.

Unlike t28hpc_hdmitx_clock_control_table_pixel_out[][] any patterns here are not obvious.

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cmsd
Contributor III

The iMX8M is driving my 1080x1920 screen now.

I've written up the details: https://stackoverflow.com/a/65812906/129805

The NXP spreadsheet is attached to this reply.  (I couldn't make use of it, as I didn't have the values it required as inputs.)

View solution in original post

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scottbrust
Contributor II

I am trying to do the same thing (add support for a custom display) and have not had any luck getting this spreadsheet from NXP. If anyone is sending them out I would like it as well

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cmsd
Contributor III

The iMX8M is driving my 1080x1920 screen now.

I've written up the details: https://stackoverflow.com/a/65812906/129805

The NXP spreadsheet is attached to this reply.  (I couldn't make use of it, as I didn't have the values it required as inputs.)

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scottbrust
Contributor II

Congrats on solving your issue, seems to be a rare thing around here  

I'm trying to understand the meaning behind your changes. In my version of the kernel (android auto 10.0.0_2.1.0 tag), the pixel timing arrays have been refactored to the following:

/* HDMI TX PLL tuning settings, pixel clock is output */
static const struct hdmi_pll_tuning imx8mq_pll_table[] = {
/*    bin VCO_freq min/max  coar  cod NDAC  PMOS PTAT div-T P-Gain Coa V2I CAL */
...
    { 11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7, 258 },
...
};

I can see the change you did was to modify "div-T". Im curious how you calculated you needed to change that to 615. 

I also saw the spreadsheet and have tried to use it to at least "validate" the pixel clock and HDMI settings im trying to support. I can input my desired pixel clock, color encoding, and color depth, but beyond that I am not sure (ie reference clock mhz, pll input divider, etc). It seems that you need to know alot about the HDMI PHY device to understand what these parameters are...

So for now I am trying to learn exactly how to go from EDID -> HDMI PHY parameters -> functional display

 

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cmsd
Contributor III

The 615 is T8_PLL_FB_DIV_TOTAL from my custom row in t28hpc_hdmitx_clock_control_table_pixel_out.

The 615 in my custom row:

{138375, 1000, 1383750, 0x03, 0x1, 0x1, 615, 0x1E8, 0x07B, 40, 0x012, 0x012, 5535000, 1, 2, 2, 2, 2, 691875, 0x2, 138375, 1},

is a linear interpolation between

{ 99000, 1000, 990000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 40, 0x012, 0x012, 3960000, 1, 2, 2, 2, 2, 495000, 0x2, 99000, 1},
 
and
 
{148500, 1000, 1485000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 40, 0x012, 0x012, 5940000, 1, 2, 2, 2, 2, 742500, 0x2, 148500, 1},
 
these being the frequencies either side of my 137,930 KHz target.
 
(I had added extra debugging to the kernel and so I knew that it was looking for T8_FEEDBACK_FACTOR of 1000.)
 
Note: from inspection:
T8_PLL_FB_DIV_TOTAL = 5 * T8_CMNDA_PLL0_FB_DIV_HIGH, and
T8_CMNDA_PLL0_FB_DIV_LOW = (T8_CMNDA_PLL0_FB_DIV_HIGH - 1) * 4
 
My custom line required a fractional value of T8_CMNDA_PLL0_FB_DIV_HIGH (which is not possible) so I picked 123 over 122 as it was nearer (+0.3% vs -0.5%).
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scottbrust
Contributor II

Thanks for the explanation. I'm assuming you are using an IMX8MQ? I am using an IMX8QM, which looks like it has a different table for HDMI timings and a different HDMI "PHY". I can see my pixel clock frequency (50mhz) is defined in a "range" in this table: 

 

/* HDMI TX clock control settings, pixel clock is input */
static const struct hdmi_ctrl imx8qm_ctrl_table[] = {
/*pclk_l  pclk_h  fd    DRR_L    DRR_H   PLLD */
{ 
...
{ 42500,  85000, 1000,  425000,  850000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 4, 0x02,  42500,  85000},
...
};

 

I can see these PHY parameters are selected for my supplied pixel clock in hdmi_phy_cfg_ss28fdsoi (I think in imx8mq it calls hdmi_phy_cfg_t28hpc instead). Everything looks "valid", I get no error messages but the display just doesnt work. So I think my issue isnt that there is no timing defined, but rather the timing "range" defined  for my pixel clock generates invalid parameters for the PHY. I think this is where that spreadsheet might come in handy for me... 

Thanks again for your replies.

 

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cmsd
Contributor III

Yes, I'm using an iMX8M with four cores, which could well be the Q.  Good luck with finding a solution.

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miketubby
Contributor I

@weidong_sun

Please can you post a link to the HDMI Pixel Clock Calculation spreadsheet as the link on the forum does not work?

Dead link is:

https://community.nxp.com/servlet/JiveServlet/download/1224555-1-458676/HDMI%20-%20pixel%20clock%20c...

 

Alternatively can you email me the spreadsheet?

 

Regards

Mike

 

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miketubby
Contributor I

I think there is a spreadsheet called HDMI - pixel clock calculation.xlsx that does this work, if NXP can send it to you.

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