Continuing with my countdown of top reasons to use i.MX RT1010 crossover MCU, today I want to talk about performance. The performance of the i.MX RT series really pushes this portfolio to a classification of its own – crossover MCUs. Engineers can now enjoy the level of performance historically seen in the processor space, now in the MCU world – providing tremendous familiarity and usability for engineers. But just ask the rabbit from the Tortoise and the Hare fable, sometimes it is not enough just to be fast. You have to be smart too. Within the i.MX RT1010 family, several smart features are coupled together with the 500 MHz Arm® Cortex®-M7 core. These features include:
16 KB L1 instruction cache
8 KB L1 data cache
Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
Support the Armv7-M Thumb instruction set, defined in the ARM v7-M architecture
Integrated MPU, up to 16 individual protection regions
Up to 128 KB I-TCM and D-TCM in total
While all of these features are important to designers, the large amount of tightly-coupled memory (TCM) is one of the most important and is a hidden hero of MCU performance. TCM is a small, dedicated memory region that, as the name implies, is very close to the CPU. The CPU can access the TCM every single cycle, and TCM provides the highest possible theoretical performance.
For MCUs with only a small amount of TCM, the data must be stored in embedded flash or in an external NOR or NAND flash instead. Therefore, for every access that the CPU core has to make to a non-TCM, there is a significant degradation in the effective performance as the CPU must wait for several cycles for the data to arrive.
Conversely, i.MX RT crossover MCUs with high density of on-chip TCM delivers significantly higher net effective performance than what is possible with other traditional MCUs. So, not only will you benefit from high 500 MHz performance, you will benefit from efficient, smart performance as well.
Want to learn more about i.MX RT Series, read this white paper.