[i.MX6ULL][Storage] eMMC

[Seunghui]

Dear NXP,

This is seunhui Lee from SEC.

I'm responsible for eMMC storage driver.

I have several question about storage.

I've checked the kernel log.

bus speed : DDR mode

clock speed : 33MHz

Is it correct? And plus, Is it the maxium host bus speed?

Thanks and regards,

Seunghui Lee.

[AldoG]

Hello,

Yes it is correct, one could check the reference manual chapter 58.1.2.1 Data Transfer Modes:
• Identification Mode (up to 400 kHz)
• MMC full speed mode (up to 26 MHz)
• MMC high speed mode (up to 52 MHz)
• MMC HS200 mode (up to 200 MHz)
• MMC DDR mode (52 MHz both edges)

Regarding the maximum speed, we de have an errata for this: ERR010450 MMC: EMMC can only run under or equal to 150 MHz

uSDHC driver in BSP limits the highest clock to 150 MHz for EMMC HS200 and SD/SDIO 3.0 SDR104 at 1.8 V.
uSDHC driver in BSP limits the highest clock to 45 MHz for EMMC DDR52 and SD/SDIO DDR50 at 1.8 V.

Best regards,
Aldo.

[Seunghui]

Dear Aldo,

So, it supports HS200 mode with 150MHz.
As I checked it, BSP's released DDR mode by default. ( 4 bits bus mode not 8 bits )
Is there any reason for that? ( any problem ? )
If possible, could you guide to change HS200 mode for it ?

Thanks and regards,
Seunghui Lee.

[AldoG]

Hi,

I would like to know, which BSP version you’re working with?
Also, regarding the imx6ull support HS200 mode, for the 8bit support, you need to make  i.MX6ULL emmc controler and emmc flash powered 1.8V.

Best regards,
Aldo.

[Seunghui]

Dear NXP,

How can I check BSP version for this?
Once I set bus-width = <8> in dts file, it seems to work 8-bit mode.

Is it correct setting and acceptable?

* imx6ull_chagerhub.00.dtb.reverse.dts

mmc@2194000 {
<snip>
bus-width = <0x08>;