lx2160ardb mc load in uboot

[jiaxiaobo]

Hi NXP. I am doing 16g ddr read and write test under uboot. I find that mc will be copied to ddr 0x23e0000000 and loaded before I test ddr, and modify a discontinuous address at the beginning of 0x23e0121f60 when I read and write ddr. However, ddr test in my other lx2160 project is also loaded after mc, but mc does not affect ddr test. Is there any configuration I have ignored?

The boot part is printed as follows:

NOTICE: BL2: v2.4(release):00ab20e28-dirty
NOTICE: BL2: Built : 09:59:00, Aug 27 2024
NOTICE: Fixed DDR on board
NOTICE: DDR PMU Hardware version-0x1210
NOTICE: DDR PMU Firmware vision-0x100d (vA-2020.06-SP1)
NOTICE: DDR4 UDIMM with 1-rank 64-bit bus (x16)

NOTICE: 16 GB DDR4, 64-bit, CL=19, ECC on, 256B
NOTICE: BL2: Booting BL31
NOTICE: BL31: v2.4(release):00ab20e28-dirty
NOTICE: BL31: Built : 09:59:08, Aug 27 2024
NOTICE: Welcome to lx2160ardb BL31 Phase

U-Boot 2020.04 (Aug 27 2024 - 09:58:41 +0800)

SoC: LX2160AE Rev2.0 (0x87361020)
Clock Configuration:
CPU0(A72):1800 MHz CPU1(A72):1800 MHz CPU2(A72):1800 MHz
CPU3(A72):1800 MHz CPU4(A72):1800 MHz CPU5(A72):1800 MHz
CPU6(A72):1800 MHz CPU7(A72):1800 MHz CPU8(A72):1800 MHz
CPU9(A72):1800 MHz CPU10(A72):1800 MHz CPU11(A72):1800 MHz
CPU12(A72):1800 MHz CPU13(A72):1800 MHz CPU14(A72):1800 MHz
CPU15(A72):1800 MHz
Bus: 700 MHz DDR: 2600 MT/s
Reset Configuration Word (RCW):
00000000: 486b6b38 20480048 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 02a001a0 00002580 00000000 24000000
00000030: 09250411 00000001 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027008 00000000
00000070: 00670030 00152022
Model: NXP Layerscape LA1224-RDB Board
Board: LA1224-RDB, Fail to select IO expander from I2C Bus
Board version: ?, boot from failed to select IO expander
FlexSPI NOR
Fail to select IO expander from I2C Bus
SERDES1 Reference: Clock1 = 100MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
Fail to select IO expander from I2C Bus
Fail to select IO expander from I2C Bus
PCA: failed to get udev : -121
Fail to select IO expander from I2C Bus
PCA: failed to get udev : -121
core voltage not adjusted
DRAM: 15.9 GiB
DDR 15.9 GiB (DDR4, 64-bit, CL=19, ECC on)
DDR Controller Interleaving Mode: 256B
PCA: failed to get udev : -121
WDT: Started with servicing (30s timeout)
Using SERDES1 Protocol: 7 (0x7)
Using SERDES2 Protocol: 3 (0x3)
Using SERDES3 Protocol: 0 (0x0)
SERDES3[PRTCL] = 0x0 is not valid
MMC: FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected gd25lx256e with page size 256 Bytes, erase size 64 KiB, total 32 MiB
*** Warning - bad CRC, using default environment

EEPROM: Read failed.
In: serial_pl01x
Out: serial_pl01x
Err: serial_pl01x
Fail to select IO expander from I2C Bus
Fail to select IO expander from I2C Bus
gpio: pin MPC@2320000_15 (gpio 79) value is 0
calc checksum:0x0, checksum_etag:0xffffffff
board etag checck fail
Net: start to init rtl8363
data: 0x6511
switchChip: 2
rtl8363 init complete
0x80 0x0 0x3f 0x0 0x0 0x0 0x0
uboot from slave flash
SerDes1 protocol 0x7 is not supported on LA1224RDB
PCIe1: pcie@3400000 disabled
PCIe2: pcie@3500000 disabled
PCIe3: pcie@3600000 Root Complex: no link
PCIe4: pcie@3700000 Root Complex: no link
PCIe5: pcie@3800000 disabled
PCIe6: pcie@3900000 disabled
DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth0) using random MAC address - 0e:e1:36:50:41:c7
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth1) using random MAC address - 2a:3f:97:c6:33:91
, DPMAC5@xgmii
Warning: DPMAC5@xgmii (eth2) using random MAC address - ea:77:e1:cb:7b:6b
, DPMAC6@xgmii
Warning: DPMAC6@xgmii (eth3) using random MAC address - 7e:d8:05:3d:fc:3b
, DPMAC7@sgmii
Warning: DPMAC7@sgmii (eth4) using random MAC address - 2e:72:1f:cc:b6:2d
, DPMAC8@sgmii
Warning: DPMAC8@sgmii (eth5) using random MAC address - f6:29:4f:e2:ce:1d
, DPMAC9@sgmii
Warning: DPMAC9@sgmii (eth6) using random MAC address - 96:ab:f7:9f:7a:4f
, DPMAC10@sgmii
Warning: DPMAC10@sgmii (eth7) using random MAC address - f6:b0:79:52:df:d3
, DPMAC17@rgmii-id [PRIME]
Warning: DPMAC17@rgmii-id (eth8) using random MAC address - 9e:ae:b4:3d:24:95

SF: Detected gd25lx256e with page size 256 Bytes, erase size 64 KiB, total 32 MiB
device 0 offset 0x640000, size 0x80000
SF: 524288 bytes @ 0x640000 Read: OK
device 0 offset 0xa00000, size 0x300000
SF: 3145728 bytes @ 0xa00000 Read: OK
device 0 offset 0xe00000, size 0x100000
SF: 1048576 bytes @ 0xe00000 Read: OK
crc32+ MC Firmware copied to address 00000023e0000000
MC DPC blob copied to address 00000023e0f00000
mc_ccsr_regs 0000000008340000

fsl-mc: Booting Management Complex ... SUCCESS
Checking access to MC portal of root DPRC container (portal_id 0, portal physical addr 000000080c000000)
fsl-mc: Management Complex booted (version: 10.37.0, boot status: 0x1)
ce_offset=0x20000, ci_offset=0x4020000, portalid=2, prios=8
Error writing to lm83 d1 high setpoint (addr=0x4c)
lm83 - lm83 command

Usage:
lm83 lm83 setcrit temp
lm83 getcrit

initr vid
soc vol 850mV cur vol 850mV
no need adjust vdd
Autoboot in 10 seconds

[yipingwang]

If mcmemsize is 0x80000000, the mcmem region is 0x23_80000000 - 0x24_00000000, the firmware address always is 0x23_e0000000.

Please use mtest to test memory from 0x23_80000000 - 0x24_00000000 in u-boot.

[jiaxiaobo]

Hi yipingwang:

the mcmemsize is always 0x70000000 in lx2160a_common.h .  mcmemsize is also 0x70000000 in our other project. I can't understand another engineering problem without this ddr aging being affected by MC.

thanks xiaobo.

[yipingwang]

In your case, please use mtest to test memory from 0x23_80000000 - 0x24_00000000 in u-boot.

[jiaxiaobo]

Hi yipingwang:

I looked at the use of mtest online. This is basically an example of running mtest in the uboot console. Are there any use examples or documentation in c code for reference?

thanks xiaobo.