Thanks for the response, JC. If I understand you correctly, the FSCI implementation in the stack itself is fine. I'm ultimately going to control the MKW41Z on my board with a K64, does the FSCI implementation there have the same issue?
I haven't had a chance to look at the shell demo, but I now have a custom board in-house with the MKW41Z512VHT4 on it, and I'm trying to get back to the point where I'm able to join it to the same network as one of my FRDM boards, but I'm having some issues with it. I'm able to create a network on the KW41-FRDM board, and connect to it from my custom board, but it doesn't work the other way around, when my device behaves as a leader/commissioner. I hadn't changed any of the build flags, so I went through the definitions in the KDS project tonight and updated them to match my hardware, but nothing changed.
The KW41z on my board will create a network, establish itself as leader/commissioner, and responds with success to adding an expected joiner, syncing the steering data, and getting that expected joiner. The DTLS session starts as well, but ultimately fails with JoinerDtlsError. The documentation only suggests that this might be an incorrect PSKd, but I've verified that the expected joiner command specifies "kinetis" (all commands being sent to create the network and configure the commissioner on the custom board are identical to the ones sent to the FRDM board) and the FRDM board is running the app with only the build config modifications I made earlier (in my first post), not the other flag changes I made tonight (disabling LEDs, buttons, TSI, keyboard).
One thing I did have to do on my custom board was set the CLOCK_INIT_CONFIG to CLOCK_RUN_32, as with the default value (CLOCK_RUN_48_24) was hanging in CLOCK_SetFeeMode (called from BootToFeeMode) while waiting for IREFST to change. My design is basically the same as the FRDM board, but without the DCDC components (running bypass), and with a 32MHz osc (the FRDM schematic says 32MHz, but has a 27.648MHz xtal mounted), at 10ppm tolerance/stability (50/NA on the FRDM part), and 10pF load. (I just now noticed that frequency discrepancy, I guess that's why it's hanging). I also see that the config I'm using now is BLPE, and the core clock is 32MHz, vs a comment that says the config for the FRDM board is 48MHz. Maybe that's the issue.
I've put a breakpoint in the APP_Commissioning_Handler while debugging from my board, which is a switch statement on the parameter code. Regardless of the value passed in, if I put a breakpoint in the case for the JoinerError and the JoinerDtlsError (a common case) it is always hit.
So is there any way I can get more detail on this DTLS failure? Or maybe I've missed a build flag I need to set to account for my different oscillator speed?
Thanks,
Ben