The question of SPI configuration in half duplex mode of KW45 chip

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The question of SPI configuration in half duplex mode of KW45 chip

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Taiyi
Contributor I

Hello !

         Recently in debugging the SPI peripheral of the KW45 chip, KW45 as the host, there are three SPI slave devices. There is a host that needs to communicate with a half-duplex core and a full-duplex device.

         Excuse me:

        1、 half duplex mode SPI host how to configure the initial core port port, I configured the mode half duplex communication failed.

        2.、There is an SPI that communicates with full-duplex core and duplex device at the same time. How should it be configured? Is the data sent by referring to half-duplex to communicate with full-duplex device?

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @Taiyi 

For the SPI configuration and working mode, you can refer to our  KW45 Reference Manual, Chapter 48 Low Power Serial Peripheral Interface (LPSPI)

And after reading this part, if you still have any question, we can discuss further.

 

Best regards,

Christine.

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Taiyi
Contributor I

Hello !

         I would like to ask if the SPI configuration as follows can work in half duplex mode, output mode and pin configuration? Is full duplex compatible with half duplex?企业微信截图_16928393077143.png

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @Taiyi 

Can you please let me know your SDK version and which example are you using?

Where do you find this screenshot?

 

Best regards,

Christine.

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Taiyi
Contributor I

HI !

企业微信截图_16929439857935.png企业微信截图_16929439092241.png企业微信截图_16929437902677.pngThis is the code I ported from the official DEMO "freertos_lpspi", I use the routine "digital_key_car_anchor_freertos" this routine. We now use our own KW45 circuit board to debug the peripheral SPI chip, which must work in half-duplex mode. But we used this SPI code to debug with the slave, and the communication received data was wrong. When communicating with a full-duplex device, data is received and sent normally. Therefore, I would like to consult whether I need to modify the underlying configuration of SPI in half-duplex dual-mode.

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @Taiyi 

Can you please check whether the Master side has masked tx data in half duplex mode(fsl_lpspi.c) and debug according to the configurations in KW45B41Z83.h

LPSPI_MasterTransferNonBlocking() and  LPSPI_MasterTransferBlocking() function.

/* Mask tx data in half duplex mode */
if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) &&
(transfer->txData == NULL))
{
stateParams.isTxMask = true;
}

/* Mask tx data in half duplex mode since the tx/rx share the same pin, so that the data received from slave is not
* interfered. */
if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) &&
(handle->txData == NULL))
{
handle->isTxMask = true;
}

 

#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
/*! PINCFG - Pin Configuration
* 0b00..SIN is used for input data; SOUT is used for output data.
* 0b01..SIN is used for both input and output data. Only half-duplex serial transfers are supported.
* 0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are supported.
* 0b11..SOUT is used for input data; SIN is used for output data.

 

Best regards,

Christine.

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Taiyi
Contributor I

May I ask where the SPI host side configs the half-duplex mode? I have changed the send mask Settings, but it seems that the data can not be sent now. Whether the SPI host needs to send 0xFF data when receiving data in half-duplex mode.

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @Taiyi 

Would you mind share what changes did you do?

And have you tried according to my previous comment?

 

Best regards,

Christine.

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @Taiyi 

Any updates?

 

Best regards,

Christine.

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Christine_Li
NXP TechSupport
NXP TechSupport

Hi, @Taiyi 

Any updates?

 

Best regards,

Christine.

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Taiyi
Contributor I

Hello, The SPI problem is solved, it is my protocol processing problem.

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Christine_Li
NXP TechSupport
NXP TechSupport

HI, @Taiyi 

Thanks for your feedback.

Would you mind to share your experience or fix solution details to us?

So that we can learn something from this case. 

 

Best regards,

Christine.

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