NHS3152 SPI Slave (IRQ Based) how to clear TX FIFO and put data into TX FIFO?

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NHS3152 SPI Slave (IRQ Based) how to clear TX FIFO and put data into TX FIFO?

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SilabS
Contributor II

When MCU is set up as SPI Slave in IRQ mode (non blocking), the data are sent from TX FIFO on every CLK coming from a master. The problem here is that on every CLK edge, a bit is sent from TX FIFO out on SPI lines and a bit is pulled into TX FIFO from a defined TX Buffer specified over a struct provided in API.

To specifiy more. Let us imagine the following situation. We want to get some data from a master and based on the data that we got, we send some data back. (basically command-answer)

While the data are being received from master on RX line and RX FIFO, from TX FIFO some data are being sent out. The data that are being sent out are ignored so that is not a problem. The problem is that some data is being simultaniously pulled into TX FIFO from a predefined TX Buffer which is somewhere in memory. This data is something that we do not want to send to the master. Only when we receive all the data, we want to send our answer to master when master send CLK. We can set the pointer to TX Buffer where our wanted data is stored. But TX FIFO is already prepended with some data which are pulled in during receive. And that data we do not want to send at all.

Now the question is how to clear TX FIFO of this prepended data which are pulled in during receive or any clock that comes from master?

I already tried to use sendFrame method from API which should put some bytes into FIFO. Although that would not be solution or an answer to my question, even that did not work. I even tried to do complete reinitialization of SPI module since after SPI module is initialized the data are being pulled into TX FIFO from a defined TX Buffer. This of course will not perform good in runtime so this is not an option and it did not work for me.

So what I basically need is:

How to first clear TX FIFO (in hardware)? How afterwards to put/pull correct data into TX FIFO manually?

Unfortunately in the API there is no word about this. In a documentation which I looked at I have found nothing.

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SilabS
Contributor II

Hello @estephania_mart , thank you for late reply.

So here is the thing. I believe that not me, or any other user should have to DEBUG how the chip works. That should be written in the documentation! Here, that is not the case!

While there is lot of information written about protocol signals, how they should look like in different protocol formats, the information how exactly the SPI module works is somewhat obscure. Namely, the module desciptions in the Documentation are on basic level and the examples provided in API Documenation (which your html link points to) are really basic. The infomation how something works exaclty, cannot be obtained from there. To add to that, how a module works with some specific settings would not be bad to have in the documentation.

So that is really something that NXP could work on. Improve the documenation.

Now lets get to the problem.

Chip_SSP_Int_FlushData() is not of any help. Since if one has TX half empty IRQ active, when the TX FIFO is being flushed, half way this IRQ will be triggered and a new batch is loaded. Also turning this IRQ off is not an option since one needs it for data to be loaded into FIFO. (There is no direct way to flush TX FIFO)

The key is in coordination between RX half full and TX half empty IRQs. If one wants to receive some amount of data and after some time when the clock comes, send a response, after recive the TX half full has to be turned off.

The following lines could be used in SPI IRQ handler to implement the stated.

if((sspSetupExample2.rx_cnt >= sspSetupExample2.length))
{

//disable TX half empty IRQ
NSS_SSP0->IMSC &= ~SSP_TXIM;
sspSetupExample2.rx_data = bufferSwitch;
sspSetupExample2.rx_cnt = 0;

}
if(sspSetupExample2.tx_cnt >= sspSetupExample2.length)
{
//disable TX half empty IRQ, enable RX half full and Timout IRQ
NSS_SSP0->IMSC |= SSP_RXIM;
NSS_SSP0->IMSC |= SSP_RTIM;
NSS_SSP0->IMSC &= ~SSP_TXIM;
}

Also one should not by any mean turn on TX half empty IRQ in IRQ Handler. sspSetupExample2.tx_cnt >= sspSetupExample2.length does not depict that the data have been clocked out of TX FIFO. After setting a buffer to send the data, g_sspSetup.rx_cnt >= g_sspSetup.length would depict when the data is sent.

One would have to test it and Debug it by itself to get how it exactly works.

I hope this could be helpful to someone.

Regards

Silabs

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2 Replies
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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

 

By any chance, have you checked the Chip_SSP_Int_FlushData()? By any chance, is this whats you are looking for ?

Could you please try checking this html file ?

release_mra2_nhs3100/release_mra2_12_4_nhs3100/docs/firmware/a00490.html

I believe that you will find a good guidance on the SPI usage there

 

Regards,

Estephania

0 Kudos
57 Views
SilabS
Contributor II

Hello @estephania_mart , thank you for late reply.

So here is the thing. I believe that not me, or any other user should have to DEBUG how the chip works. That should be written in the documentation! Here, that is not the case!

While there is lot of information written about protocol signals, how they should look like in different protocol formats, the information how exactly the SPI module works is somewhat obscure. Namely, the module desciptions in the Documentation are on basic level and the examples provided in API Documenation (which your html link points to) are really basic. The infomation how something works exaclty, cannot be obtained from there. To add to that, how a module works with some specific settings would not be bad to have in the documentation.

So that is really something that NXP could work on. Improve the documenation.

Now lets get to the problem.

Chip_SSP_Int_FlushData() is not of any help. Since if one has TX half empty IRQ active, when the TX FIFO is being flushed, half way this IRQ will be triggered and a new batch is loaded. Also turning this IRQ off is not an option since one needs it for data to be loaded into FIFO. (There is no direct way to flush TX FIFO)

The key is in coordination between RX half full and TX half empty IRQs. If one wants to receive some amount of data and after some time when the clock comes, send a response, after recive the TX half full has to be turned off.

The following lines could be used in SPI IRQ handler to implement the stated.

if((sspSetupExample2.rx_cnt >= sspSetupExample2.length))
{

//disable TX half empty IRQ
NSS_SSP0->IMSC &= ~SSP_TXIM;
sspSetupExample2.rx_data = bufferSwitch;
sspSetupExample2.rx_cnt = 0;

}
if(sspSetupExample2.tx_cnt >= sspSetupExample2.length)
{
//disable TX half empty IRQ, enable RX half full and Timout IRQ
NSS_SSP0->IMSC |= SSP_RXIM;
NSS_SSP0->IMSC |= SSP_RTIM;
NSS_SSP0->IMSC &= ~SSP_TXIM;
}

Also one should not by any mean turn on TX half empty IRQ in IRQ Handler. sspSetupExample2.tx_cnt >= sspSetupExample2.length does not depict that the data have been clocked out of TX FIFO. After setting a buffer to send the data, g_sspSetup.rx_cnt >= g_sspSetup.length would depict when the data is sent.

One would have to test it and Debug it by itself to get how it exactly works.

I hope this could be helpful to someone.

Regards

Silabs

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