NFC PN7150 Internal Assert issue

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

NFC PN7150 Internal Assert issue

Jump to solution
2,270 Views
dominusdrr
Contributor IV

Hi.

I have a problem very similar to this thread, but with some differences

How to solve NFC PN7150 Internal Assert issue. 

In the same way I am sending an RF field generation:

0x21 0x03 0x09 0x04 0x00 0x01 0x02 0x01 0x01 0x01 0x06 0x01 (Star Discovery)

I then get an appropriate response from the NFC:

0x41 0x03 0x01 0x00 (RF_DISCOVER_RSP)

And then a CORE Reset notification

0x60 0x00 0x06 0xA0 0x00 0xB1 0xAB 0x20 0x00 (CORE_RESET_NTF)

It seems to me that it is different from the thread mentioned, since I do get a correct response to Star Discovery and the fields after 0xA0 in CORE_RESET_NTF are not equal to zero.

Any suggestion or comment?





0 Kudos
1 Solution
2,236 Views
dominusdrr
Contributor IV

Hi

It seems that I discovered the error.

I began to analyze each one of the frames that the DH sends and the PN7150 responds until I reach the clock configuration (NXP_CLK_CONF)

I was configuring as PLL

uint8_t NxpNci_CLK_CONF[] = 
{ 
0x20, 0x02, 0x09, 0x02, /* CORE_SET_CONFIG_CMD */ 
0xA0, 0x03, 0x01, 0x11, /* CLOCK_SEL_CFG */ 
0xA0, 0x04, 0x01, 0x01 /* CLOCK_TO_CFG */ 
};

But my hardware uses a 27.12MHz crystal and the setting must be Xtal

uint8_t NxpNci_CLK_CONF[] = { 
0x20, 0x02, 0x05, 0x01, /* CORE_SET_CONFIG_CMD */ 
0xA0, 0x03, 0x01, 0x08 /* CLOCK_SEL_CFG */ };

 

I thought that this mistake was not going to solve the problem, but after correcting it and checking just in case the error was repeated, to my surprise, it works fine. 

View solution in original post

1 Reply
2,237 Views
dominusdrr
Contributor IV

Hi

It seems that I discovered the error.

I began to analyze each one of the frames that the DH sends and the PN7150 responds until I reach the clock configuration (NXP_CLK_CONF)

I was configuring as PLL

uint8_t NxpNci_CLK_CONF[] = 
{ 
0x20, 0x02, 0x09, 0x02, /* CORE_SET_CONFIG_CMD */ 
0xA0, 0x03, 0x01, 0x11, /* CLOCK_SEL_CFG */ 
0xA0, 0x04, 0x01, 0x01 /* CLOCK_TO_CFG */ 
};

But my hardware uses a 27.12MHz crystal and the setting must be Xtal

uint8_t NxpNci_CLK_CONF[] = { 
0x20, 0x02, 0x05, 0x01, /* CORE_SET_CONFIG_CMD */ 
0xA0, 0x03, 0x01, 0x08 /* CLOCK_SEL_CFG */ };

 

I thought that this mistake was not going to solve the problem, but after correcting it and checking just in case the error was repeated, to my surprise, it works fine.