Hello @mzl
I hope you are doing very well.
NXP recommends VBAT should be tied to VDDREG if not used.
It can be the reason:
Have you tried tying VBAT to VDDREG?
Best regards,
Salas.
On our design, the VDD33_LDOIN, VDDREG, VDD33, VDDA33_ADC, VREFH_ADC, VDDA33_AFE are tied together and supplied by 3.3V DC power supply.
VDD12_AFE, VDD are tied tether and supplied by 1.2V DC power supply.
VBAT is left to be float.
I also measured the power up sequence of 3.3V DC power supply and 1.2V DC power supply.
The 1.2V DC power supply rise to 1.0V is about 60us earlier than the 3.3V power supply rise to 3.0V.
Based on the processor hardware requirement, this power up sequence does not meet the requirement.
While when I still leave the VBAT to be float. and tried with 3.3V DC power supply comes up about 4ms earlier than 1.2V DC power supply. Then the CPU may start up.
I also tried another testing: add a coin battery (3.2V) for the VBAT, and still keep the wrong power up sequence of the 3.3V power supply and 1.2V power supply (1.2V power supply comes up about 60 us earlier than 3.3V power supply). The CPU may also startup.
Now I am confused, which one is the actual root cause? VBAT shall be tied with VDDREG / coin battery, or correct power up sequence of 3.3V power supply and 1.2V power supply
Hello @mzl
Based on the MVF61 hardware design guidelines, the issue you're encountering is most likely due to a violation in power-up sequence requirements, rather than VBAT being left floating.
But also, you can see on datasheet, VBAT must be tied to VDDREG if not used:
Best regards,
Salas.
