Hello fengwei
I think the DCU offset is wrong. This was found previously by vincent.aubineau
currently is:
#define DCU_CLUT_OFFSET | 0x0000500 |
But should be:
#define DCU_CLUT_OFFSET | 0x0000200 |
According to the reference manua rev 4
"The CLUT/Tile RAM is mapped in the DCU4 32K memory space from address 0x2000
to 0x3FFF. This gives 2048 entries, which provides up to eight full CLUTs for 8 bpp
layers."
Can we have this Change Request for the next release 0.6.0 of the drivers?
Thanks,
Ioseph
Solved! Go to Solution.
Ioseph,
Sure. Thank you for your kind mention.
Regards,
Feng Wei