Vybrid and CP15SDISABLE

[billpringlemeir]

How is the ARM CP15SDISABLE connected on the Vybrid devices.  This is referred to in the ARM cortex-A5 MPCore TRM version r0p1 in table 4-1 on page 4-3.  It lists the following CP15 registers as locked by this signal.

• SCTLR System Control Register
• ACTLR Auxiliary Control Register
• TTBR0 Translation Table Base Register
• TTBCR Translation Table Base Control Register
• DACR Domain Access Control Register
• PRRR, NMRR Memory region remap
• VBAR Vector Base Address Register
• MVBAR Monitor Vector Base Address Register

The Vybrid bootloader/HAB could set this signal or perhaps it is available via some other module?  Or it is hard coded in the Vybrid design?

[RossMcLuckie · Accepted solution]

I replied to this via Outlook yesterday, no idea why it hasn't updated, anyway, confirmed with design, on Vybrid CP15SDISABLE has been tied low, so not configurable.

Ross

[RossMcLuckie]

Bill,

Can I ask what is your interest in using CP15SDISABLE, can't say I'm familiar with all these registers, but I know the VBAR is accessible and programmable, so would suggest these registers are not locked out in Vybrid, do you have a need or desire to do this, is it a problem if not possible?

Ross

[timesyssupport]

Hi Bill,

I could not find anywhere in u-boot 2011.12 for Vybrid that used this signal. Some of the registers mentioned are accessed at arch/arm/cpu/armv7/start.S and arch/arm/cpu/armv7/vybrid/.

Thanks,

Timesys Support

[billpringlemeir]

Thanks, it is not a register directly accessible by the Vybrid.  CP15SDISABLE is an external signal to the Cortex-A5 core.  There is no documentation on how it is routed on the Vybrid.  Ie, it is a ARM referenced signal and only Freescale design could know how they hooked it up; or I missed something in the documentation.  I guess that if it is accessible, it would be through some register or it is just tied off as unused (Ie, these CP15 registers can always be modified).  It could be through the MSM, the SNVS, the CSU, the NIC, something else?

[timesyssupport]

Hello Bill,

Yes, I did not see any documentation about how CP15SDISABLE was routed on the Vybrid. Freescale design would need to answer this.

Thanks,

Timesys Support

[karina_valencia]

RossMcLuckie can you add your comments about it?

[karina_valencia]

timesyssupport can you  attend this case?