The RM is not 100% clear on whether it can support DD3 with 8 bit bus or not.
A couple of sections mention both 8 and 16 bits, but one table 2-2 (page 102) only stated 16 bits.
Can you help me clarify whether Vybrid support DDR3 with 8bit data bus?
A datasheet is the main document describing a component, and below is excerpt from the Vybrid datasheet:
"– 8/16 bit DRAM Controller with support for LPDDR2/DDR3 up to 400 MHz (ECC supported for 8-bit only and not 6-bit)".
(BTW, expecting the follow-up question :smileyhappy: -- used in the 8-bit mode are the 8 lower bits of the 16-bit DRAM controller's bus.)
Regards, Naoum Gitnik.
I'd like to add to the question if Vybrid support 2 DDR3 x8 with one as low byte and the other for upper byte. The address and control lines will have double load due to two DDR3. Is it OK? Please confirm. Thx
Dear Quinn ,
I guess you are asking not about the case when two 8-bit memory chips are connected (essentially in parallel on the data bus) to make it look as though it is one 16-bit memory chip, but two independent 8-bit ones.
To deal with two 8-bit memory chips independently, a processor should have 2 independent sets of address lines and 'chip selects', which Vybrid, unfortunately, does not have, as per its datasheet.
I actually want to have two 8-bit DDR3 devices in parallel mode as a single 16-bit DDR3 bus. My concern is if Vybrid has any issue with ADDR and CTRL drives a double load. Thanks.
Dear Quinn ,
At the first glance, "ADDR and CTRL drives a double load" does not look like a problem from the loading point of view. The memory chips' inputs are of a CMOS type, i.e., no real DC load, and double capacitance quite likely may be compensated by boosting the Vybrid output drive strength.
However, you have to take into account that, based on the market trend, all our 16-bit DDR Vybrid-based design examples are based on a single 16-bit DDR chip, which means you will have to develop the board layout fully on your own, without benefiting from our results. You will have to follow examples for other processors - those using multiple DDR chips, e.g., i.MX6 family, including consulting the relevant published Hardware Development Guide, which has a DDR section board-layout chapter.