Hello,
I am a newbie in I2S interface for audio codec chips. I need to connect a codec WM8974 of Cirrus/Wolfson, which has a mono audio speaker and a microphone. The WM8974 has the following digital I/O pinout:
I2S Interface:
- ADCDAT (O): ADC digital audio data output
- DACDAT (I): DAC digital audio data input
- FRAME (I/O): DAC and ADC sample rate clock or frame sync
- BCLK (I/O): Digital audio port clock
- MCLK (I): Master clock input
Control Interface (2-Wire / 3-Wire):
- CSB/GPIO (I/O): 3-Wire MPU chip select or general purpose input/output pin.
- SCLK (I): 3-Wire MPU clock Input / 2-Wire MPU Clock Input
- SDIN (I/O): 3-Wire MPU data Input / 2-Wire MPU Data Input
- MODE (I): Control interface mode selection pin.
In one hand, I am going to set the Control Interface to 2-Wire (MODE=low) in order to use the Vybrid I2C interface (SCLK / SDATA). This is quite easy.
On the order hand, regarding the I2S interface, if I am going to use the codec as slave, theoretically, I will connect the Vybrid as follows:
Vybrid Codec
--------- --------
SAIx_RX_DATA <---- ADCDAT
SAIx_TX_DATA ----> DACDAT
SAIx_TX_BCLK ----> BCLK
SAIx_TX_SYNC ----> FRAME
If I connect the audio codec as master, the pinout connection will be:
Vybrid Codec
--------- --------
SAIx_RX_DATA <---- ADCDAT
SAIx_TX_DATA ----> DACDAT
SAIx_RX_BCLK <---- BCLK
SAIx_RX_SYNC <---- FRAME
My question is if these connections are OK for use of the SAI/I2S interfaces (SAI0, SAI1, ...) of the Vybrid VF6xx.
Kind Regards,
Juan.
Hi Juan,
>Can you tell me which value has tsys?
According to the WM8974 wolfson audio codec document - ESAI (enhanced serial audio interface) clock cycle(Tssicc) = 30ns.
S12 is i2s_BCLK pulse width high (S11) and pulse width low (S11) - which is approximately 130ns. Please refer the attached tabular column.
Thanks,
Timesys support.
timesyssupport please continue with the follow up.
Dear,
In Document Number VYBRIDFSERIESEC appears S11 is 4*tsys. Can you tell me which value has tsys"?
Thank you in advance.
Hi Juan,
Selection between the two wire and 3 wire can be done using Mode bit. If MS=1 3-wire mode is selected and viceversa.
In the master mode (MS bit set to 1), clock signals BCLK, and FRAME can be outputs when the WM8974 operates as a master and BCLK, FRAME can be inputs when the WM8974 operates as a slave (MS bit set to 0) as you given.
As per the WM8974 audio codec document the above given configuration should work.
Thanks,
Timesys support.
timesyssupport can you take this case?