Vybrid VF50 BootROM fuse bank CRC checking

[jansimak]

Hi,

we use SoC module Colibry VF50 produced by Toradex - module contains VF50 MPU, a NAND flash and a DDR3 ram.

With original configuration from Toradex the MPU works properly. Original configuration uses ext.oscilator ( i.e. OSC_BYPASS fuse is not blown ).

Problem is that when an ext.oscilator clock failure occurs ( just temporary failure ) then MPU freeze forever ( testing can be done in u-boot ). So we configured the MPU to reset it when FOSC is less than 40MHz - register SRC_SICR[CMU_OLR]. It works as expected, but we have another issue.

When MPU resets and ext.oscilator is not working properly BootRom enters into safe fail mode - serial download ( ref.manual 7.5.4.3 Clocks at Boot Time ).

We intended to avoid this with blowing of OSC_BYPASS fuse. After the OSC_BYPASS fuse is blown, the MPU after reset / power up always enters to serial download mode immediately and we have no idea why.

Could problem be that we modified only OSC_BYPASS fuse and didn't modify CRC for given fuse bank? Does the VF50 BootROM do checking of the fuse bank CRC?

When BootROM decides to enter fail safe mode ( serial download ) - is the failure reason stored as an error code in a register - to have possibility to get it and analyze it?

Thank you.

[kef2]

• we configured the MPU to reset it when FOSC is less than 40MHz - register SRC_SICR[CMU_OLR]. It works as expected

I think you refer to CMU_OLR bit description on page 850 VFxxx RM Rev.0 10/2016:

• Configures CMU event of FOSC frequency less than 40 Mhz

This must be wrong and rudiment from older manual perhaps for different chip. First of all oscillator clock is 24MHz on Toradex, so how would it help comparing to 40MHz? It is also contrary to Figure 6-2. CMU Block Diagram:

As you may see OLRI compares internal 24MHz oscillator (FIRC) to external oscillator (FXOSC), which is 24MHz for Toradex module. 2^RCDIV is 1,2,3 or 4. So in the best case you can compare external FXOSC (24MHz) to FIRC/2 (12MHz). (BTW did you enable clock monitor? OLRI, FHHI and FLLI don’t work without enabling CMU). 24 vs 12MHz is a big frequency step! Since all apps operate at high PLL clocks, also PLLs with removed source clock usually operate for a while until going totally into the weeds, I think you should compare bus clock to internal/external oscillator. Comparison borders should be set quite narrow. As soon PLL and bus clock drifts, reset using SRC_SIRC or fire interrupt on failure to switch in ISR immediately back to internal oscillator and try to recover.

Edward