Vybrid Reset Behavior

[ericaverill]

Hi,

I'm seeing the following behavior of the RESETB signal when I toggle a SW reset using the SW_RST bit in the SRC_SCR register. I believe the Vybrid (MVF51) is the source of this behavior. Any ideas of what might be causing multiple short resets followed by the longer one? This is a very repeatable occurrence when I toggle a SW reset.

[ericaverill]

I have some further information and I believe I have found the root cause of this issue.

During operation we are running the core off a 1.2V switching supply which we switch over to during boot. This switchover circuit is a make-before-break circuit with ~1ms of crossover time controlled by a single Vybrid GPIO which defaults to the Vybrid's internal LDO. When we issue a SW reset all of the GPIOs default to inputs causing the external pull on the core select IO to switch the core supply back to the Vybrid's LDO. This causes a small step in the core supply voltage as the two supplies are not exactly the same voltage. The Vybrid doesn't seem to like this during reset. I've tested switching during operation many times before (even though we don't plan on doing it) and we switch every boot and have never seen an issue. We've confirmed that If we switch the supply then issue the SW reset command I no longer see the multiple resets.

Note that we are seeing different values in the reset status register (SRC_SRSR) depending on what we do as well that was causing some other problems:

1. Power On Reset: 0x00FEFF65 (expected)

2. SW Reset without Switching supplies beforehand: 0x00001201 (unexpected)

3. SW Reset after Switching to the Vybrid's LDO: 0x00040000 (expected)

So I believe I have some new questions:

1. Is this behavior expected? Is it indicating a different design issue?

2. How long should I wait after switching supplies before issuing the SW reset command?

Below are some scope captures for further information:

Reset signal (green) and core supply (purple) when issuing a SW reset without switching the core supply first:

Reset signal (green) and core supply (purple) when issuing a SW reset after switching the core supply. Note that you can see the supply switchover towards the end of the capture:

Detailed captures of the core supply when switching between the LDO and switching supply. In this case the LDO seems to be at a slightly higher voltage (~50mV) than the switching supply:

[cyborgnegotiato]

jiri-b36968​ could you please look at it?

[karina_valencia]

jiri-b36968​ can  continue with the follow up until next week.

[karina_valencia]

Jiri Kotzian do you have an update?

[jiri-b36968]

Hello Eric,

VDD voltage range is 1.16V - 1.26V. On the first picture we can see voltage drop more than 100mV. So for sure we are out of specification and voltage was lower than expected. The spike does down to about 1.1V:

This confirms also result of SRC_SRSR 0x00001201:

• Indicates event POR1- power on reset
• Indicates HP regulator's LVD event
• Indicates ULP regulator's LVD event

Using of external DC/DC is an option but it is not recommended exactly because of this kind of complications. Better way to save energy is to use 1.5V DC/DC and supply external ballast with 1.5V instead of original 3.3V. This is done on reference board - TWR-VF65 rev.H.

Voltage levels have to improved, better filtered/timed or recommended circuit have to be used.

/Jiri

[ericaverill]

Jiri,

I agree that the spike you circled is clearly out of the limit but that's already after abnormal things have begun to happen. It appears that our 1.2V switcher is being dragged down during reset I believe because the Vybrid is drawing more power than the supply was designed for (we designed it for a lightly loaded processor as that's our use case). In any case switching back to the LDO first seems to have solved the issue. What I still was wondering though is if there is a stabilization time required for the LDO before we reset?

[jiri-b36968]

Hi Eric,

the spike was incorrect for sure, but the level before it was also in area of "not sure".

Inside the chip are low voltage detectors - yes they have small filter, but cannot say what is the time constant. Do you need this information?

/Jiri

[ericaverill]

Jiri,

Given that switching before reset seems to be working fine I think we are just trying to verify that we are waiting long enough between switching back to the LDO and resetting the part. Based on the captures above the LDO seems to stabilize in <1ms. We are currently delaying 10ms between the switchover and reset which would seem like long enough with margin, would you agree?

[karina_valencia]

jiri-b36968​ please continue with the follow up.

[karina_valencia]

jiri-b36968​ do you have an update?

[jiri-b36968 · Accepted solution]

Hi Eric,

I tend to agree. Please check BCTRL pin  which controls external ballast transistor. This will show you the reaction of internal circuit. Also ensure max 2.5V and 20ma  - more in DS rev.8 chapter 6.2.1.5.

/Jiri

[timesyssupport]

Hello Eric,

Our support is limited to Linux on VF6xx; we have only recently begun efforts porting Linux to VF5xx. It seems this is better suited to the Freescale Automotive Vybrid team at this time, until such time as Linux support is available for VF5xx; can you confirm/assist karinavalencia​?

Thank you,

Timesys Support

[karina_valencia]

cyborgnegotiator​ can you comment please?

[GordyCarlson]

Karina,  thanks for your efforts.  Jozef may be out or unable to respond.  Is there an alternate resource in the Vybrid apps group this can be forwarded to?   best, Gordy

[cyborgnegotiato]

Hi Gordy,

sorry for delay, could you please specify where you measured this signal? If it is custom board, please check other ICs connected on RESETB signal.

I checked RESETB on our TWR-VF65GS10, and I can see only one short pulse on reset.

Regards,

Jozef

[karina_valencia]

timesyssupport​ can you  attend this case?