Hi,
The RM is incorrect and will be updated in the next version. The MCR register is at offset 0x0.
-Anthony
Hi Stephanie,
The RM should be correct. In the latest RM, the offset states 0xf00 as well. Where in the QuadSPI_load example are you seeing the offset of 0x0? Possibly I have an updated version.
Hope this helps,
Lydia
Hi Lydia,
thanks for checking this. I'm seeing the offset of 0x0 in the file MVF50GS10MK50.h. This is the reference the DS-5 tools I'm using found for the assignment QuadSPI0->MCR from the quadspi.c file. I'll paste the section from the MVF50GS10MK50.h file below.
Our board is a custom board which is based on the TWR-VF65GS10 Schematics (Rev G) schematics.
/* ----------------------------------------------------------------------------
-- QuadSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/**
* @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
* @{
*/
/** QuadSPI - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[4];
__IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */