A quick update. We are attempting to read out the DRAM in my debugger (ULinkpro D in ARM DS-5). In essence what we are doing is break during our memory test, which writes a familiar pattern (0xAA) to a pre-defined address range (starting at 0x8000_0000).
What we are seeing is that, even while stopped, the DRAM seems to be periodically changing (see attached). What may cause this?
/Tom
Figure: ARM DS-5 memory view with auto-update at 1s intervals while debugger stopped at breakpoint.
Hi jiri-b36968
There are no noticeable changes.
To help illustrate the issue described above, I have included a screenshot (below). The test SW has just finished testing the even data-lines and move on to testing the odd data lines. The memory view is taken from when the MCU stopped at the first readback of the odd-datalines test (no other DRAM reads have been executed after last write).
As you can see, 0xAA-pattern (with errors) is turning into the new intended pattern 0x55 as we get further away from 0x8000_0000. When refreshing the memory view, the whole memory view grows into 0x55 (without errors).
/Tom
Hello Thomas,
I'm afraid that you are right - differential lines are swapped.
As source of confusion DRAM DS shows three different label pairs for the clock
- CK_t / CK_c
- CK / CK#
- CK / /CK
DRAM DS:
Vybrid DS
Our old validation board confirms it:
DDR_CLK0 = MCK_H0 = CK_T
/DDR_CLK0 = MCK_L0 = CK_C
Memory:
Vybrid:
/Jiri
