Vybrid L2 cache latency too optimistic in Toradex device tree

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Vybrid L2 cache latency too optimistic in Toradex device tree

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Contributor III

I'm using a Phytec PCM052 with Toradex kernel 4.0. The product is close to release, so I did tests at higher temperatures. At about 80°C CPU temperature I got a kernel panic because of unresolved memory access, and the system wouldn't reboot. u-boot tried to load the kernel, but it immediately hang. For some reason the Timesys 3.13 kernel still worked at higher temperatures. It took me a while to find out why, but here's the solution. The latency of the L2 cache has been reduced in the Toradex device tree.

Timesys:

   arm,data-latency = <4 2 3>;
   arm,tag-latency = <4 2 3>;

Toradex:

    arm,data-latency = <1 1 1>;
   arm,tag-latency = <2 2 2>;

When I change the latency back to the old values, the Toradex kernel also works fine at high temperatures.

Best regards

Michael

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